To meet industry demands for increased levels of integration as well as improved performance, bandwidth, latency, power, weight and form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking utilizing Through Silicon Via (TSV) chip to chip interconnects. "TSV technology is on the cusp of enabling transformative performance improvements, power reductions and dense package sizes for applications ranging from handheld mobile devices to high-end servers," said Mian Quddus, Chairman of the JEDEC Board of Directors.
The Solid State Memories Committee (JC-42) has been working since June 2008 on definitions of standardized 3D memory stacks for DDR3 which provide power and performance benefits a full generation ahead of conventional technology. The DDR4 standard will be implemented with 3D support from the start.
The Multiple Chip Packages Committee (JC-63) is currently developing mixed technology pad sequence and device package standards. An active Task Group of the Low Power Memories Subcommittee (JC-42.6) is developing standards for Wide I/O Mobile Memory with TSV interconnect stacked on System on a Chip (SoC) Application Processors.
The Silicon Devices Reliability Qualification & Monitoring Subcommittee (JC-14.3) has been working on reliability interactions of 3D stacks and has released JEP158: 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Understanding and Evaluating Reliability Interactions. In addition, reliability test methods developed by JC-14.1 and JC-14.2 and quality documents developed by JC-14.4 are applicable to 3D-IC packaged and unpackaged evaluations and qualifications.
The Mechanical Standardization Committee (JC-11) has been working since June 2010 on Wide I/O Mobile Memory package outline standardization, including an active Task Group focused on Design Guide and MO creation.
JEDEC invites technology and product developers from interested companies and organizations worldwide to participate.