According to the recently released program for the conference, Intel will talk about the upcoming 32nm "Westmere" processors ("Westmere: A Family of 32nm IA Processors"). Westmere is a family of next-generation IA processors for mobile, desktop and server segments on a second-generation high-κ metal-gate 32nm process. Dual-core versions of the architecture are already shipping, while six-core server versions are expected to hit the market in June.
The new 32nm Westmere chips are offering increased core count, cache size, and frequency within same power envelope as the previous generation with further improvements in power efficiency, a set of new features, and support for low-voltage DDR3.
Intel's six-core Westmerepacks 1.17 billion transistors, uses a 12 MByte shared L3 cache and supports low-voltage DDR3 memory. Intel's paper will additionally describe a new anti-resonance feature of Intel's QuickPath Interconnect that lowers jitter.
Intel's "rival" AMD will also present a paper ("An x86-64 Core Implemented in 32nm SOI CMOS") describing the 32nm implementation of an AMD x86-64 core occupying 9.69mm2 and containing more than 35 million transistors (excluding L2 cache). The CPU operates at frequencies >3GHz and the core incorporates numerous design and power improvements to enable an operating range of 2.5 to 25W and a zero-power gated state that make the core well-suited to a broad range of mobile and desktop products.
AMD's 32nm CPU is expected to be available in 2011. According to the ISSC program, it is not clear which core will AMD describe in its paper. The company's 32nm designs shipping in 2011 include two new cores and some existing ones moved to a 32nm process. As the company outlined last week, it plans to release the low-power "Bobcat" core positioned against Intel's Atom design as well as the "Bulldozer" high performance core for both desktop and servers.
For now, the company is expected to compete with Intel with a host of 45nm processors including Magny Cours which will pack two six-cores dice in a single 12-core package for PC servers.
Intel also plans to present two more papers at the event. The first one ("A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS") will describe a 567mm2 processor on 45nm CMOS that integrates 48 IA-32 cores and 4 DDR3 channels in a 6?4 2D-mesh network. Cores communicate through message passing using 384KB of on-die shared memory. Finegrain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. As performance scales, the processor dissipates between 25W and 125W.
The company will also describe an on-die multi-core circuit-switched network that achieves 2.64Tb/s throughput for an 8?8 2D mesh, consuming 4.73W in 45nm CMOS at 1.1V and 50°C. Pipelined circuit-switched transmission, circuit channel queue circuits and dual supplies enable up to 1.51Tb/s/W energy efficiency, with scalable streaming performance of 6.43Tb/s.
Separately, IBM will introduce the POWER7, the next generation processor of the POWER family. The 8-core chip will support 32 threads and it is implemented in 45nm 11M CMOS SOI. The 32kB L1 caches feature 1 read port banked write for the I-cache and 2 read ports banked write for the D-cache. The on-chip cache hierarchy consists of a 256kB fast, private SRAM L2 and a 32MB shared L3, implemented in embedded DRAM.
The company will also describe a "64-thread simultaneous multi-threaded processor that uses architecture and implementation techniques to achieve high throughput at low power." Although it is not clear which processor is described here, teqniques such as static VDD scaling, multi-voltage design, clock gating, multiple VT devices, dynamic thermal control, eDRAM and a low-voltage circuit design reduce power by >50% in a 428mm2 chip. The worst-case power is 65W at 2.0GHz, 0.85V, according to the paper.
Finally Sun will describe the "Rainbow Falls" chip, a 16-core SPARC SoC processor that enables up to 512 threads in a 4-way glueless system to maximize throughput. The 6MB L2 cache of 461GB/s and the 308-pin SerDes I/O of 2.4Tb/s support the required bandwidth. Six clock and four voltage domains, as well as power management and circuit techniques, optimize performance, power, variability and yield trade-offs across the 377mm2 die.
The International Solid State Circuits Conference will be held february 7-11 in San Francisco, CA. For additional information, visit http://www.isscc.org/isscc/index.htm.