Draft Specifications Of Hybrid Memory Cube Interface Released
The Hybrid Memory Cube Consortium (HMCC), led by Micron Technology and Samsung today announced that its developer members have released the initial draft of the Hybrid Memory Cube (HMC) interface specification.
Issuance of the draft puts the consortium on schedule to release the final version by the end of this year. The industry specification will enable adopters to fully develop designs that leverage HMC's technology, which has the potential to boost performance in a wide range of applications.
The initial specification draft consists of an interface protocol and short-reach interconnection across physical layers (PHYs) targeted for high-performance networking, industrial, and test and measurement applications. The next step in development of the specification calls for the consortium's adopters and developers to refine the specification and define an ultra short-reach PHY for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs.
"With the draft standard now available for final input and modification by adopter members, we're excited to move one step closer to enabling the Hybrid Memory Cube and the latest generation of 28-nanometer (nm) FPGAs to be easily integrated into high-performance systems," said Rob Sturgill, architect, at Altera. "The steady progress among the consortium's member companies for defininOg a new standard bodes well for businesses who would like to achieve unprecedented system performance and bandwidth by incorporating the Hybrid Memory Cube into their product strategies."
Micron and Samsung, the initial developing members of the HMCC, are working closely with Altera Corporation, ARM, HP, IBM, Microsoft, Open-Silicon, Inc., SK hynix Co., and Xilinx, Inc., to allow HMC to pave the way for a wide range of advances in electronics.
As envisioned, HMC capabilities will leap beyond current and near-term memory architectures in the areas of performance, packaging and power efficiencies, offering a major shift from present memory technology.
One of the primary challenges facing the industry -- and a key motivation for forming the HMCC -- is that the memory bandwidth required by high-performance computers and next-generation networking equipment has increased beyond what conventional memory architectures can efficiently provide.
The term "memory wall" has been used to describe this challenge. Breaking through the memory wall requires an architecture such as HMC that can provide increased density and bandwidth with significantly lower power consumption.
The final interface specification is scheduled for completion and release by the end of 2012.
The initial specification draft consists of an interface protocol and short-reach interconnection across physical layers (PHYs) targeted for high-performance networking, industrial, and test and measurement applications. The next step in development of the specification calls for the consortium's adopters and developers to refine the specification and define an ultra short-reach PHY for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs.
"With the draft standard now available for final input and modification by adopter members, we're excited to move one step closer to enabling the Hybrid Memory Cube and the latest generation of 28-nanometer (nm) FPGAs to be easily integrated into high-performance systems," said Rob Sturgill, architect, at Altera. "The steady progress among the consortium's member companies for defininOg a new standard bodes well for businesses who would like to achieve unprecedented system performance and bandwidth by incorporating the Hybrid Memory Cube into their product strategies."
Micron and Samsung, the initial developing members of the HMCC, are working closely with Altera Corporation, ARM, HP, IBM, Microsoft, Open-Silicon, Inc., SK hynix Co., and Xilinx, Inc., to allow HMC to pave the way for a wide range of advances in electronics.
As envisioned, HMC capabilities will leap beyond current and near-term memory architectures in the areas of performance, packaging and power efficiencies, offering a major shift from present memory technology.
One of the primary challenges facing the industry -- and a key motivation for forming the HMCC -- is that the memory bandwidth required by high-performance computers and next-generation networking equipment has increased beyond what conventional memory architectures can efficiently provide.
The term "memory wall" has been used to describe this challenge. Breaking through the memory wall requires an architecture such as HMC that can provide increased density and bandwidth with significantly lower power consumption.
The final interface specification is scheduled for completion and release by the end of 2012.
