Toshiba started to mass-produce products using 15nm process technology in April 2014 and is planning to shift to the products during the period from 2014 to 2015.
Toshiba's next step is to will shift to the BiCS (bit cost scalable) technology, which three-dimensionally stacks memory cells, instead of further scaling down the process. The company plans to start to use the BiCS for volume production in early 2016, Naruke said.
Toshiba's plan already positions the Japanese company behind Samsung Electronics, which has already started volume production of 3D NAND.
The goal for the company is to achieve a lower production cost of BiCS products compared to that of 15nm-process products. The number of stacked memory cell layers should be increased, and the throughput of etching and CVD (chemical vapor deposition) equipments should be also improved, Naruke added.
Toshiba aims to stack much more than 30 memory cell layers but doubling the current throughput will take at least a year from now.
Toshiba will temporarily switch to 3D by mass-producing BiCS products to build a cushion and, then, consider scaling down process by using new lithography equipment, Naruke said. Specifically, it will consider applying EUV (extreme ultraviolet) lithography and nanoimprint lithography for scaling down the interconnection layer and underlayer, aiming to realize a super-high capacity with a combination of 3D and scaling.
"EUV lithography is stuck with a problem of improving the output of light source. Nanoimprint lithography has not yet reached a level equivalent to EUV lithography (in terms of technology evaluation for volume production). But we will accumulate various kinds of data for volume production in cooperation of equipment makers for about a year from now. We will have a clearer vision of dimensions (sizes) for volume production and so on in 2015 or 2016," Naruke said.
Toshiba is also considering using BiCS for five to six years from now, but after 2020, ReRAM (resistive random-access memory) and ion (magnetic wall displacement type) memory are candidates for use. Naruke said those new memories would be manufactured using three-dimensionally stacking layers, with scaling beyond 10nm.