Infineon Announces 90nm Hard Disk Drive Read Channel Core HDDs
Infineon Technologies AG today announced availability of a hard disk drive read channel core, an integrated circuit implemented in the company's 90 nanometer process technology.
Developed in cooperation with Hitachi Global Storage Technologies, the read channel core is a milestone on the path to developing high-integration controller chips for next generation hard disk drives.
"Migration to 90nm of the Infineon read channel core enables the HDD industry to meet next generation product requirements, including higher data rates, reduced power consumption and smaller die-size leading to advanced SOC solutions at competitive cost. The first tested read channel core silicon has demonstrated that the PLL is able to reach up to 3.6GHz speed and that the Analog Front-End signal path allows for datarates up to 2.7Gb/s. This is an increase of approx. 50% compared to advanced Read Channels in 130nm technologies," said Sandro Cerato, General Manager and Vice President at Infineon ADS - ASIC and Design Solutions.
The new read channel technology generation supports features such as perpendicular recording and leverages on 2nd generation Reverse Concatenation coding to deliver increased signal-to-noise-ratio (SNR) performance for improved storage densities.
A second implementation, currently in development for battery operated applications, targets a low power dissipation. It will also provide high stand-by power and leakage current performance thanks to Infineon?s 90nm process technology that is designed to support handheld applications such as cellular phones.
Fabs currently offering Infineon's 90nm technology include Infineon's Dresden fab in Germany and UMC in Taiwan.
"Migration to 90nm of the Infineon read channel core enables the HDD industry to meet next generation product requirements, including higher data rates, reduced power consumption and smaller die-size leading to advanced SOC solutions at competitive cost. The first tested read channel core silicon has demonstrated that the PLL is able to reach up to 3.6GHz speed and that the Analog Front-End signal path allows for datarates up to 2.7Gb/s. This is an increase of approx. 50% compared to advanced Read Channels in 130nm technologies," said Sandro Cerato, General Manager and Vice President at Infineon ADS - ASIC and Design Solutions.
The new read channel technology generation supports features such as perpendicular recording and leverages on 2nd generation Reverse Concatenation coding to deliver increased signal-to-noise-ratio (SNR) performance for improved storage densities.
A second implementation, currently in development for battery operated applications, targets a low power dissipation. It will also provide high stand-by power and leakage current performance thanks to Infineon?s 90nm process technology that is designed to support handheld applications such as cellular phones.
Fabs currently offering Infineon's 90nm technology include Infineon's Dresden fab in Germany and UMC in Taiwan.
