SK hynix, which has already developed 16Gb (Gigabits) DDR5 (Double Data Rate 5) DRAM, will start mass producing it this year.
DDR5 can offer more than two times the bandwidth compared to DDR4. This is important in order to process the intensive data generated by technologies including big data, artificial intelligence (AI), and machine learning, which are leading the 4th Industrial Revolution.
The company is preparing DDR5 that supports more than twice the DDR4’s 3200Mbps. When developing DDR5, the goal was to achieve more than 4800Mbps, which would be a more than 50% increase of the bandwidth per DIMM.
In order to increase the memory bandwidth more than twice compared to DDR4, the amount of data processed within the same unit of time must be doubled. DDR5 will provide increased performance, capacity, and power and cost efficiency previously not available to DDR4, and various features are adopted in DDR5 to support the increase of memory bandwidth.
Firstly, DDR5 adopted 32banks structure based on 8 bank groups, which is twice as many as DDR4’s 16banks structure using 4 bank groups. This helped double DDR5’s memory access availability compared to DDR4.
Secondly, DDR5’s burst length (BL) is increased to 16 compared to 8 of DDR4, which is another key feature to double memory access availability.
Thirdly, DDR4 cannot perform other operations while refreshing, so it cannot be accessed from the system during refresh timing. However, DDR5 adopted Same Bank Refresh function, allowing the system to access other banks when certain banks are operating, thus improving memory access availability.
Lastly, there are many difficulties in terms of signal integrity with the large number of channels and DIMMs/Sockets in the server system. However, by adopting a Decision Feedback Equalization (DFE) circuit, which eliminates reflective noise during the channels’ high-speed operation, DDR5 increased the speed per pin considerably.
DDR5 also provides a power-efficient design and improved reliability features, while delivering increased performance compared to DDR4.
First of all, with an operating voltage of 1.1V, lowered from DDR4’s 1.2V, DDR5 aims to reduce power consumption per bandwidth by more than 20% of its predecessor.
On-die error correction code (ECC) and error check and scrub (ECS), which were first to be adopted in DDR5, also allow for more reliable technology node scaling by correcting single bit errors internally. Therefore, it is expected to contribute to further cost reduction in the future. ECS records the DRAM defects and provides the error counts to the host, thereby increasing transparency and enhancing the reliability, availability, and serviceability (RAS) function of the server system.