Samsung has certified Cadence's custom and analog/mixed-signal (AMS) IC design flow for the 5LPE process technology, along with Cadence's reference flow for the creation of 8LPP automotive designs and the company's 3D-IC advanced packaging integration flow for the 7LPP process.

Custom/AMS Flow Certified for Samsung 5LPE Process Technology

Samsung and Cadence collaborate to deliver an integrated flow for designing analog and mixed-signal applications at the 5nm node. Cadence's custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundry’s 5nm Low-Power Early (5LPE) process technology. This certification ensures mutual customers of Cadence and Samsung Foundry have immediate access to a highly automated circuit design, layout, signoff and verification flow needed to design efficiently at 5LPE.

The flow enables the development of solutions using the 5LPE process for automotive, mobile, data center, artificial intelligence (AI) and other emerging applications. The tools in the flow incorporate key features that are suited for digitally assisted analog designs such as high performance, analysis and verification capabilities developed in the Cadence Spectre Accelerated Parallel Simulator (APS). Additionally, the Cadence Virtuoso Layout flow provides automation and integration.

The complete custom and AMS flow that is certified by Samsung Foundry includes the Virtuoso Analog Design Environment (ADE), Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Space-Based Router, Virtuoso Layout Suite EAD, Virtuoso Integrated Physical Verification System, Spectre APS, Voltus-Fi Custom Power Integrity Solution, Quantus Extraction Solution, Litho Physical Analyzer (LPA), LDE Electrical Analyzer (LEA) and Physical Verification System (PVS).

These tools provide allows users to perform static and dynamic circuit checks, DC/TRAN/AC/STB corner simulation, transient noise simulation, Monte Carlo simulation and high-yield estimation, electromigration and IR (EM-IR) analysis, PSS-Pnoise and reliability analysis.

They also offer users a schematic-driven layout, automated constraint-driven pin-placement and optimization, row-based device placement, layout-dependent effects (LDE) analysis and hotspot detection, automated routing with width spacing patterns (WSP) and pin-to-trunk features, electrically aware design (EAD) for reduced iterations in achieving electrically correct designs, in-design DRC verification using signoff deck and automated digital block implementation.

In addition, the tools enable parasitic extraction, custom constraint validation, post-layout simulation with Detailed Standard Parasitic Format (DSPF), full-chip DRC and layout versus schematic (LVS) signoff and design for manufacturing (DFM) pattern-matching checks for detecting and correcting litho hotspots and improving yields.

Cadence Automotive Reference Flow

Samsung Foundry has also certified a new Cadence reference flow for the creation of advanced-node automotive designs. Cadence and Samsung Foundry collaborated on the development of the reference design, which was validated using the Samsung Foundry 8nm Low-Power Plus (8LPP) process technology. The certified flow is available on a wide range of Samsung Foundry nodes and includes the Cadence digital implementation and signoff, verification and custom IC design suites, offering customers optimal power, performance and area (PPA) and a faster path to achieving automotive system-on-chip (SoC) safety, quality and reliability targets.

The certified Cadence automotive flow includes the following technologies:

• Digital and signoff suite, which enables the fastest turnaround time (TAT) and optimal design closure without expensive margins or iterations. Featuring the Innovus Implementation System, Genus Synthesis Solution, Modus DFT Software Solution, Tempus Timing Signoff Solution, Liberate Characterization Solution and the Voltus IC Power Integrity Solution, the complete RTL-to-GDSII full flow meets the requirements for automotive safety and reliability.
• Verification suite with automotive safety technology for fault campaigns, including Xcelium Parallel Logic Simulation and the JasperGold Formal Verification Platform, as well as the vManager Metric-Driven Signoff Platform, which provides a smooth transition from functional verification to an FMEDA-based flow for safety verification.
• Custom IC design suite featuring the Legato Reliability Solution, which combines the Virtuoso and Spectre technologies to overcome design roadblocks and minimize failures in the field due to manufacturing defects, device aging, electromigration, process variation, and thermal and packaging effects.

3D-IC Advanced Packaging Integration Flow

Cadence's integrated Cadence 3D-IC advanced packaging integration flow has achieved certification for the Samsung Foundry MDI (Multi-Die-Integration) packaging flow based on the 7nm Low Power Process (7LPP) technology. The reference flow provides mutual customers with a full planning, implementation and analysis flow for 3D multi-die packages.

The use of multiple stacked chips in a single package is becoming a key trend for mobile, IoT and data center designs, which is also extending into the AI and 5G market segments due to the rapid and efficient integration of complete functions that can be implemented via the optimal process node into a system in package (SiP). The Cadence technology provides analysis, implementation and physical verification capabilities within a single canvas and offers early-stage system-level pathfinding and highly-complex design capabilities for 3D signoff.

A full suite of Cadence digital and signoff as well as IC package and PCB analysis tools have been optimized for the Samsung MDI technology to guarantee integration for handling multiple dies including the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, OrbitIO interconnect designer, SiP Layout, Sigrity XtractIM technology, Sigrity XcitePI technology, Sigrity SystemSI technology, and Sigrity PowerDC technology.