The two companies started working on the joint 45-nm process development project in October 2005 and have collaborated on previous generation process development since 1998.
The current joint development project is scheduled to be completed in the middle of 2007, with volume production targeted to begin in fiscal 2008. The new 45-nm process will be used by both Matsushita and Renesas in manufacturing SoCs for advanced mobile products and networked consumer electronics products. Besides the advanced ArF immersion lithography, the companies plan to introduce other new technologies as part of the development project, including introduced-strain high-mobility transistors3 and ELK (K = 2.4) multilayer wiring modules. ELK multilayer wiring module is a multilayer copper wiring technology using interlayer insulation films with low relative permittivity.
The two companies first agreed to work together on the development of next-generation SoC technology in 1998, even before the establishment of Renesas Technology. The new project is part of the fifth stage of their collaboration, which began in October 2005. The impressive record of completed joint-development projects includes a 130-nm DRAM merged process in 2001, a 90-nm SoC process in 2002, a 90-nm DRAM merged process in 2004, and a 65-nm SoC process in 2005.