Haswell's Integrated Voltage Regulator Detailed
Besides graphics, PCI Express, and memory controllers, Intel is moving a voltage regulation into the processor with the new Haswell CPU die. Details of of this integrated Voltage Regulatios technology have been posted online.
The Chinese EXPreview website has posted leaked slides that detail the voltage regulator inside Intel's next-generation CPU.
The FIVR, or Fully Integrated Voltage Regulator, integrates legacy power delivery onto the pkg/die, simplifying the platform's power design as it consolidates 5 platform VRs found in Intel's previous CPUs, which rely on the motherboard for voltage regulation (PLL VR, IO VR, System Agent VR, Graphics VR and Processor core VR,) down to just one - the Input VR. This approach promises higher efficiency, finer granularity, and cleaner power delivery than traditional solutions. Voltage regulation for the memory is still handled separately by the motherboard, though.
The FIVR is based on a multi-cell architecture with 20 cells per chip. Each cell behaves like a regulator (25A - thermally contrained). The switching frequency of the cells is programmable between 30 and 140MHz and there are 16 power phases per cell. This results to 320 phases per chip, according to the slides.
The slides also indicate that due to the large large number of power phases, ripple (Vripple) and Thermal Drift (VTT) are minimal. Voltage ripple is "almost non-existent," with worst-case scenarios yielding no more than +/- 0.002V. The voltage drift due to temperature increases is just 0.001V. However, these figures refer to a 90nm version of the power cell. Haswell chips will be manufactured using the 22nm transistor technology.
The integrated regulator is also said to be about 50x smaller than typical VR for Intel Xeon Processor E7330 (motherboard implementaion of VR).
The FIVR, or Fully Integrated Voltage Regulator, integrates legacy power delivery onto the pkg/die, simplifying the platform's power design as it consolidates 5 platform VRs found in Intel's previous CPUs, which rely on the motherboard for voltage regulation (PLL VR, IO VR, System Agent VR, Graphics VR and Processor core VR,) down to just one - the Input VR. This approach promises higher efficiency, finer granularity, and cleaner power delivery than traditional solutions. Voltage regulation for the memory is still handled separately by the motherboard, though.
The FIVR is based on a multi-cell architecture with 20 cells per chip. Each cell behaves like a regulator (25A - thermally contrained). The switching frequency of the cells is programmable between 30 and 140MHz and there are 16 power phases per cell. This results to 320 phases per chip, according to the slides.
The slides also indicate that due to the large large number of power phases, ripple (Vripple) and Thermal Drift (VTT) are minimal. Voltage ripple is "almost non-existent," with worst-case scenarios yielding no more than +/- 0.002V. The voltage drift due to temperature increases is just 0.001V. However, these figures refer to a 90nm version of the power cell. Haswell chips will be manufactured using the 22nm transistor technology.
The integrated regulator is also said to be about 50x smaller than typical VR for Intel Xeon Processor E7330 (motherboard implementaion of VR).
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