As the first-of-its-kind memory specification for dynamic random access memory (DRAM), SPMT will initially target the mobile handset market, enabling a new generation of devices capable of running highly data intensive, media-rich applications while at the same time extending battery life.
"Serial Port Memory Technology will represent a big step forward by offering mobile handset designers the ability to expand their horizon for a new generation of products." said Jim Venable, chief technology evangelist of SPMT, LLC.
As future generations of handsets take on more functions typically seen in laptops, and as the line between cell phones and handheld media-intensive devices blur, new memory architectures will be required to handle demands for ever greater bandwidth while keeping power low and cost down.
The SPMT memory interface offers the following benefits over current parallel memory technologies:
- Pin count is reduced by at least 40 percent and often much more.
- Memory bandwidth speed capability from 1 GByte per second to at least 12 GByte per second in the current generation.
- I/O power consumption savings of approximately 50% over current DRAM technologies.
- Single- or multi-port configurations can be used on a single SPMT-enabled memory.
The SPMT Consortium was founded to provide the technology capable of delivering the bandwidth flexibility and scalability required by new generations of mobile devices, all at significantly reduced pin count, low power consumption, and at a lower cost.
The consortium?s founding members (promoters) form the governing body of the organization and are, together with contributor members, responsible for developing the SPMT specification.
Depending on the rate of industry adoption, volume production of the first SPMT-enabled prodcuts could start in the 2012 timeframe.
The SPMT promoters also announced the formation of the SPMT, LLC, the entity chartered with managing the day-to-day activities of administering the SPMT specification.