Micron Technology, Inc. began sampling the first universal flash storage (UFS) multichip package (uMCP) with low-power DDR5 (LPDDR5) DRAM.

The uMCP provides high-density and low-power storage designed to fit on slim midrange smartphone designs.

Micron UFS-based multichip packages (uMCPs) combine low-power DRAM with NAND and an onboard Universal Flash Storage (UFS) 2.1 controller controller, using 40% less space compared to a two-chip solution (PoP + discrete NAND). This optimized configuration saves power, reduces memory footprint and enables smaller smartphone designs.

“Featuring the latest LPDRAM and UFS interface, this first-in-the-industry packaging solution offers a 50% increase in memory and storage bandwidth while reducing power,” said Dr. Raj Talluri senior vice president and general manager at Micron. “Our new uMCP5 package enables midrange 5G smartphones to operate with the ultra-low latency response times and low power modes necessary to support flagship smartphone features such as multiple high-resolution cameras, multiplayer gaming and AR/VR applications.”

Micron’s uMCP5 uses 1y nm DRAM process technology and the a very small 512Gb 96L 3D NAND die. The 297-ball grid array (BGA) package supports two-channel LPDDR5 with speeds up to 6,400Mbps, a 50% performance increase over the previous-generation interface. The new package also provides the highest storage and memory density available for uMCP form factors in the market today, at 256GB and 12GB, respectively.

Micron LPDDR5 allows 5G smartphones to process data at peak speeds of up to 6.4Gbps, which is critical for preventing data-processing bottlenecks.

Micron’s uMCP5 package for LPDDR5 is available for immediate sampling.