Western Digital Corp. and Toshiba have developed their second-generation, four-bits-per-cell architecture for 3D NAND.

Implemented for the 96-layer BiCS device, the QLC technology delivers the industry's highest 3D NAND storage capacity of 1.33 terabits (Tb) in a single chip. This also realizes an unparalleled capacity of 2.66 terabytes with a 16-chip stacked architecture in one package. BiCS4 was developed at the joint venture flash manufacturing facility in Yokkaichi, Japan (WD and Toshiba Memory Corporation).

For its part, WD expects Volume shipments to commence this calendar year beginning with consumer products marketed under the SanDisk brand.
The company expects to deploy BiCS4 in a wide variety of applications from retail to enterprise SSDs.

Toshiba Memory will start to deliver samples to SSD and SSD controller manufacturers for evaluation from the beginning of September, and expects to start mass production in 2019.

"BiCS4 QLC is our second generation four-bits-per-cell device, and it builds on the learnings from our QLC implementation in 64-layer BiCS3. With the best intrinsic cost structure of any NAND product, BiCS4 underscores our strengths in developing flash innovations that allow our customers' data to thrive across retail, mobile, embedded, client and enterprise environments. We expect the four-bits-per-cell technology will find mainstream use in all these applications.," said Dr. Siva Sivaram, executive vice president, Silicon Technology and Manufacturing at Western Digital.