The company said its test wafers made through immersion lithography, have come out with as few as three defects per wafer.
The use of liquid as a medium in lithography creates, according to TSMC, a number of challenges for chip manufacturers, including defects such as bubbles, watermarks, particles, particle-induced printing defects and resist residue.
Immersion is also said to extend the life of current-generation lithography machines, used to imprint the blueprint of a chip onto the silicon wafer.
J.H. Tzeng, a spokesman for TSMC, announced that TSMC will begin manufacturing chips with feature sizes as tiny as 45-nanometers using immersion lithography, most likely in a few years.
TSMC has also recently revealed five customers for its 65-nanometer technology chips including Broadcom, Freescale Semiconductor, and Altera, which are all based in the U.S.