Toshiba's new SoC integrates 64 processor cores, eight times more than the company's multi-core SoC chip that Toshiba announced at ISSCC 2008, achieved by using tree-based network-on-chip (NoC) architecture (network-on-chip technology transfers data as packets in an SoC) and highly efficient embedded processor cores. Integrated with image recognition hardware accelerators, the new many-core SoC secures 1.5 tera operations per second at 333MHz, a processing rate 14 times faster than that of Toshiba's eight-processor multi-core predecessor.
The new SoC applies low power technologies throughout its structure, including multi-level power gating, clock gating and Toshiba's proprietary low power data-mapping flip-flop circuit. Advancing the fabrication process to 40nm secures a 40 to 50% boost in power efficiency over the company's previous multi-core chip, manufactured with 65nm process.
Toshiba plans to apply the many-core SoC and its related technologies to high performance over-HD (high definition) resolution image processing and recognition.
More details on the SoC and its development will be presented at the 2012 IEEE Symposia on VLSI Technology and Circuits in Honolulu, Hawaii on June 15.