With its architecture of NAND flash memory arranged in a matrix, Flashmatrix enables multiple data sets to be accessed in parallel and scaled linearly. All of the NAND flash memory is shared by every CPU allowing for flexibility and high performance. The entire platform is in 2U enclosure and offers linear rack scale scalability.
"Big data processing can face multiple problems in scaling, latency and power as the customer demands increase," said Ralph Schmitt, Executive of System Development at Toshiba America Electronic Components, Inc. "Flashmatrix addresses each of those issues to create a system that is a true solution for analytic processing by offering low-power-consumption, parallel processing to reduce system latency, card level scaling and a large non-volatile memory space shared by all CPUs. Flashmatrix continues Toshiba’s mission to persistently develop innovative technologies to make the best use of NAND flash memory."
TAEC will showcase Flashmatrix at booth 407 at the 2016 Flash Memory Summit, taking place August 9-11 in Santa Clara, California.