ARM announced new ARM CoreLink system IP - the CCI-550 interconnect and DMC-500 memory controller - designed to enhance system performance and efficiency in next-generation premium mobile devices. The CoreLink CCI-550 interconnect enables ARM big.LITTLE processing and a fully coherent GPU while lowering latency and increasing peak throughput. It is an improvement to the CCI-500 which ARM announced back in February among other IPs such as the new Cortex A72 core design. Both the CCI-500 and the new CCI-550 are generational successors to the CCI-400 that is found in all currently released big.LITTLE SoCs such as Samsung?s Exynos, MediaTek?s Helio or Qualcomm?s Snapdragon designs.

The improved support for GPU coherency in CoreLink CCI-550 enhances power management. Coherency reduces development costs and time for new applications accelerated by heterogeneous processing for more efficient utilization of compute engines. OpenCL 2.0 with shared virtual memory features and other newer programming models take advantage of system coherency. All processors work on the same data without unnecessary cache maintenance or memory copying. This also enables a system architecture fully aligned with the HSA (Heterogeneous System Architecture) coherency standards.

In SoC layout diagram that ARM provides, the CCI-550 is configured with two CPU clusters such as the Cortex A53 and a Cortex A72. The remaining four ACE master ports could be then dedicated to a fully coherent GPU.

ARM says that its next-generation Mali IP codenamed "Mimir" will be fully cache-coherent and would be a perfect fit to take advantage of such a configuration. Fully coherent GPUs will be able to take advantage of shared virtual memory and new simplified programmers models provided by APIs such as OpenCL 2.0 and HSA.

The CoreLink DMC-500 memory controller provides higher bandwidth and latency response for processors and display.

CoreLink CCI-550 includes improvements in the microarchitecture to deliver higher peak throughput for demanding use cases and quality of service (QoS) enhancements that reduce latency by 20 percent. SoC designers can configure the number of memory channels, tracker sizes, snoop filter capacity and scale up to 6 fully coherent processor clusters. The scalability addresses a wide range of applications beyond mobile including digital TV, automotive and cost-efficient networking applications.

Time and energy-intensive memory transactions require a memory controller designed with a system approach to reduce bottlenecks. For ARM Cortex processors, CoreLink DMC-500 offers the lowest latency and power along with enhanced QoS for LPDDR4/3 memories operating up to LPDDR4-4267 transfer speeds. When integrated at the design level, CoreLink CCI-550 and CoreLink DMC-500 work together to deliver a peak system memory bandwidth beyond 50GB/s for access to richer content such as 4K video, with predictable performance.

Performance CoreLink DMC-500

Both CoreLink products are available for licensing with production silicon expected by late 2016.