Elpida Begins Sample Shipments of DDR3 SDRAM Based on TSV Stacking Technology
Elpida Memory has begun sample shipments of the first DDR3 SDRAM (x32-bit I/O configuration) made using TSV (Through Silicon Via) three-dimensional stack packaging technology.
The sample is a low-power 8-gigabit (1-gigabyte) DDR3 SDRAM assembled in a single package that consists of four 2-gigabit DDR3 SDRAMs fitted to a single interface chip using TSV.
TSV is three-dimensional stack packaging technology, which involves stacking together multiple chips vertically through electrical connections with metal-filled via holes in the SI die. Compared with the existing connection method of wire bonding multiple chips, TSV significantly reduces the length of wires in the semiconductor design to enable faster speeds, lower power consumption, smaller package size and other important chip function advantages.
Elpida began developing TSV in 2004 based on a grant program hosted by the New Energy and Industrial Technology Development Organization (NEDO), a research endeavor founded by the Japanese government. Since then Elpida has continued to develop TSV technology. In 2009 it successfully developed the first TSV DRAM based on stacking together eight 1-gigabit DDR3 SDRAMs.
In the case of notebook PCs, Elpida believes that trial use of its 8-gigabit TSV DRAM samples will demonstrate that compared with systems that use SO-DIMM (Small-outline DIMM), operating power can be reduced by 20% and standby power by 50%. Also, the chip mounting area can be reduced by 70%, the chip height can be decreased and the DIMM socket can be eliminated.
Target applications of the new memory include tablet PCs, thin PCs and other mobile computing systems.
TSV is three-dimensional stack packaging technology, which involves stacking together multiple chips vertically through electrical connections with metal-filled via holes in the SI die. Compared with the existing connection method of wire bonding multiple chips, TSV significantly reduces the length of wires in the semiconductor design to enable faster speeds, lower power consumption, smaller package size and other important chip function advantages.
Elpida began developing TSV in 2004 based on a grant program hosted by the New Energy and Industrial Technology Development Organization (NEDO), a research endeavor founded by the Japanese government. Since then Elpida has continued to develop TSV technology. In 2009 it successfully developed the first TSV DRAM based on stacking together eight 1-gigabit DDR3 SDRAMs.
In the case of notebook PCs, Elpida believes that trial use of its 8-gigabit TSV DRAM samples will demonstrate that compared with systems that use SO-DIMM (Small-outline DIMM), operating power can be reduced by 20% and standby power by 50%. Also, the chip mounting area can be reduced by 70%, the chip height can be decreased and the DIMM socket can be eliminated.
Target applications of the new memory include tablet PCs, thin PCs and other mobile computing systems.
Comparison of Elpida's New 8-gigabit TSV DRAM with a 2-gibabyte SO-DIMM
| 2-gigabyte SO-DIMM | 8-gigabit (1-gigabyte) TSV x 2 | |
| Supply voltage (VDD) | 1.5V/1.35V | ← |
| Bust length | 8/4 | ← |
| Bank | 8 | ← |
| Cin | Cin(mono) x 8 | Cin(mono) x 2 |
| Data rate (Mbps) | 1600 (1.5V) 1066/1333 (1.35V) |
← |
| Operating (IDD1) | 1.0 | 0.8 (proportional to SO-DIMM) |
| Standby (IDD2N) | 1.0 | 0.5 (") |
| Refresh (IDD5) | 1.0 | 0.5 (") |
| Mounting area | 1.0 | 0.3 (") |
