Many others, including Arm and Globalfoundries, will act as subcontractors in the programs launched today at a San Francisco event.
The four projects are part of DARPA's Electronics Resurgence Initiative (ERI) expected to receive $1.5 billion over the next five years to drive the U.S. electronics industry forward. They aim to both serve the needs of the U.S. Department of Defense and to boost the semiconductor industry at a time of diminishing returns pursuing Moore's law to make faster, cheaper, smaller chips.
"A 53-year old exponential is unheard of - when it slows or does something different, it's incredibly frightening from a researcher's perspective," said William Chappell, who heads DARPA's microsystems office that oversees ERI. "Our goal is to impact the industry in 2025 to 2030 with research beyond what companies would be looking at today."
Other companies acting as prime contractors for the latest four projects include Applied Materials, Ferric Inc., and HRL Laboratories. In addition, researchers from Mentor Graphics and Xilinx recently joined DARPA to help manage ERI programs.
In one of the largest of the programs, Skywater Technology Foundry aims to show how it can define a monolithic 3D capability to deliver the equivalent of 7-nm chips using its base 90-nm process.
Skywater will work with researchers from MIT and Stanford on DARPA's 3DSoC program. It aims to find ways to integrate novel materials such as resistive RAMs and carbon nanotubes on a base low-temperature 90-nm process. Its success will be measured in terms of yields on devices that could slash computing times as much as 50x.
Separately, DARPA will work with Globalfoundries on MRAM and future memories in a program called Foundations Required for Novel Compute (FRANC).
Among the four new programs, FRANC aims to find new materials and devices to make 10x advances in embedded, non-volatile memories as fast as SRAM but more dense. Prime contractors include Applied Materials, Ferric, HRL, and academics at UCLA and the Universities of Minnesota and Illinois.
Intel, Nvidia, and Qualcomm are prime contractors for the Software-Defined Hardware (SDH) program. They will work with researchers at Georgia Tech, Princeton, Stanford, and the Universities of Michigan and Washington.
SDH aims to define chips that can be reconfigured in real time based on the data being processed. Devices from both SDH and the FRANC program will be measured by the size and speed of graphs that they traverse.
DARPA awarded the NVIDIA team a four-year contract worth up to $23 million under the new SDH program. The team includes researchers from NVIDIA, Massachusetts Institute of Technology, University of Illinois at Urbana-Champaign and University of California, Davis. It plans to demonstrate innovative technologies in hardware and software prototypes during the program.
"The Electronics Resurgence Initiative jump-starts innovations to address the challenges stemming from the end of Moore's law," said Steve Keckler, vice president of Architecture Research at NVIDIA. "The technologies that are developed through the ERI program will have a substantial impact on the future of electronic computing devices and NVIDIA's future products."
NVIDIA will also collaborate with Cadence Design Systems to apply machine learning algorithms to design automation flows as part of DARPA's new Intelligent Design of Electronic Assets (IDEA) program.
The program aims to develop a fully automated "no human in the loop" circuit layout generator that enables users with no electronic design expertise to complete physical design of electronic hardware. This effort will add to NVIDIA's ongoing research into high-productivity integrated circuit design methodology under the DARPA Circuit Realization at Faster Timescales (CRAFT) program.
One other program, Domain-Specific System on Chip (DSSoC), will include IBM, Oak Ridge National Labs, Arizona State, and Stanford. It aims to find ways to balance applications-specific and general-purpose processing techniques starting with work on software-defined radio. As the project matures, it aims to handle multiple types of accelerators.
The four new programs are part of six programs announced last fall.
As part of the programs announced last month, Cadence said that it will work with Carnegie Mellon and Nvidia to define a design flow for chips and boards that can use machine learning.