Altera and Micron Demonstrate First FPGA and Hybrid Memory Cube
Altera and Micron Technology have jointly demonstrated successful interoperability between Altera Stratix V FPGAs and Micron?s Hybrid Memory Cube (HMC).
This technology achievement enables system designers to evaluate today the benefits of HMC with FPGAs and SoCs for next-generation communications and high-performance computing designs. The demonstration provides an early proof point that production support of HMC will be delivered with Altera's Generation 10 portfolio, in alignment with market timing, and includes both Stratix 10 and Arria 10 FPGAs and SoCs.
HMC has been recognized as an answer to address the limitations imposed by conventional memory technology, and provides ultra-high system performance with significantly lower power-per-bit. HMC delivers up to 15 times the bandwidth of a DDR3 module and uses 70 percent less energy and 90 percent less space than existing technologies. HMC's abstracted memory allows designers to devote more time leveraging HMC's revolutionary features and performance and less time navigating the multitude of memory parameters required to implement basic functions. It also manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation. Micron expects to begin sampling HMC later this year with volume production ramping in 2014.
Arria 10 FPGAs and SoCs are the first device families in the Generation 10 portfolio and will be the first devices to support HMC technology in volume production. Leveraging an enhanced architecture optimized for TSMC's 20 nm process, Arria 10 FPGAs and SoCs will use HMC to extend the benefits by providing both 15 percent higher core performance than today's highest performance Stratix V FPGAs and up to 40 percent lower power compared to the lowest power Arria V midrange FPGAs. Arria 10 FPGAs and SoCs will offer up to 96 transceiver channels.
Stratix 10 FPGAs and SoCs will enable the advanced, high performance applications across communications, military, broadcast and compute and storage markets. These high-performance applications often require the highest memory bandwidth, which drives the need for an HMC-ready architecture. Leveraging Intel's 14 nm Tri-Gate process and an enhanced high-performance architecture that integrates with HMC technology, Stratix 10 FPGAs and SoCs will enable system solutions with an operating frequency over one gigahertz, and two times the core performance of current high-end 28 nm FPGAs.
Altera Stratix V FPGAs are available now in volume production. First samples of Arria 10 devices will be available in early 2014, with Quartus II design software support available now in early access. Altera will have 14 nm Stratix 10 FPGA test chips in 2013 and design software support in 2014.
HMC has been recognized as an answer to address the limitations imposed by conventional memory technology, and provides ultra-high system performance with significantly lower power-per-bit. HMC delivers up to 15 times the bandwidth of a DDR3 module and uses 70 percent less energy and 90 percent less space than existing technologies. HMC's abstracted memory allows designers to devote more time leveraging HMC's revolutionary features and performance and less time navigating the multitude of memory parameters required to implement basic functions. It also manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation. Micron expects to begin sampling HMC later this year with volume production ramping in 2014.
Arria 10 FPGAs and SoCs are the first device families in the Generation 10 portfolio and will be the first devices to support HMC technology in volume production. Leveraging an enhanced architecture optimized for TSMC's 20 nm process, Arria 10 FPGAs and SoCs will use HMC to extend the benefits by providing both 15 percent higher core performance than today's highest performance Stratix V FPGAs and up to 40 percent lower power compared to the lowest power Arria V midrange FPGAs. Arria 10 FPGAs and SoCs will offer up to 96 transceiver channels.
Stratix 10 FPGAs and SoCs will enable the advanced, high performance applications across communications, military, broadcast and compute and storage markets. These high-performance applications often require the highest memory bandwidth, which drives the need for an HMC-ready architecture. Leveraging Intel's 14 nm Tri-Gate process and an enhanced high-performance architecture that integrates with HMC technology, Stratix 10 FPGAs and SoCs will enable system solutions with an operating frequency over one gigahertz, and two times the core performance of current high-end 28 nm FPGAs.
Altera Stratix V FPGAs are available now in volume production. First samples of Arria 10 devices will be available in early 2014, with Quartus II design software support available now in early access. Altera will have 14 nm Stratix 10 FPGA test chips in 2013 and design software support in 2014.
