SiS Announces SiS168 120Hz/100Hz Motion-Fluent Co-processor for LCD-TV
Silicon Integrated Systems Corp.(SiS), today unveiled a new
120Hz/100Hz Motion-Fluent Co-processor -- SiS168, to decrease the
motion-blur artifacts in typical holding type display like TFT
LCD.
The Motion-Fluent Co-processor can also ultimately reduce the
film-judder usually seen in the low frame rate movie, SiS said.
The SiS168 adopts a close-loop Multi-state Motion Vector Search & Analysis (MMVSA) algorithm to increase the reliability and accuracy of the regenerated motion vectors. The closed loop MMVSA algorithm includes moving objects grouping, moving object boundary detection, static text detection, motion vector distribution analysis, and motion vector regeneration. The low frame rate films with inverse 3:2/2:2 pull-down is also detected during the motion vector distribution-analysis. Based on the motion vectors, new frame is thus elaborated and inserted between two originally consecutive frames, with further polish such as de-blocking, halo effect reducing, and low frame-rate film-processing.
SiS168 can easily pair with a series of SiS HDTV SoC processors, such as SiS328, SiS329, the upcoming new generation SiS HDTV products or any other 3rd party TV chips to upgrade motion-video picture quality. It accepts either Single-link LVDS (WXGA) or Dual-link LVDS (Full-HD) input signals and outputs to either Dual-link LVDS (WXGA) or Quad-link LVDS (Full-HD) 100Hz/120Hz TFT LCD panel. Besides, SiS168 can detect and convert the 24 or 30 FPS films to judder-free scenes when displayed in 50Hz/60Hz LCD panels. The SiS168 also includes a color management function of SiS Digital Native Video Engine technology (DNVETM), offering a flexibility to enhance the color performance on the converted picture frames.
SiS 168 is equipped with both the I2C bus, and SPI bus to easily adapt to HDTV system board or T-CON panel board, respectively. Besides, to accelerate the board-level EMI-compliance convergence, SiS168 supports the Spread Spectrum mechanism on the Quad-link LVDS bus and Dual-channel DDR2-1066 bus, respectively.
SiS 168 employs 0.11um 3.3V/1.2V silicon process, and is housed in a 484 LFBGA package. Engineer sample is available now for designing and validating and mass production is expected to start in May, 2009, SiS said.
The SiS168 adopts a close-loop Multi-state Motion Vector Search & Analysis (MMVSA) algorithm to increase the reliability and accuracy of the regenerated motion vectors. The closed loop MMVSA algorithm includes moving objects grouping, moving object boundary detection, static text detection, motion vector distribution analysis, and motion vector regeneration. The low frame rate films with inverse 3:2/2:2 pull-down is also detected during the motion vector distribution-analysis. Based on the motion vectors, new frame is thus elaborated and inserted between two originally consecutive frames, with further polish such as de-blocking, halo effect reducing, and low frame-rate film-processing.
SiS168 can easily pair with a series of SiS HDTV SoC processors, such as SiS328, SiS329, the upcoming new generation SiS HDTV products or any other 3rd party TV chips to upgrade motion-video picture quality. It accepts either Single-link LVDS (WXGA) or Dual-link LVDS (Full-HD) input signals and outputs to either Dual-link LVDS (WXGA) or Quad-link LVDS (Full-HD) 100Hz/120Hz TFT LCD panel. Besides, SiS168 can detect and convert the 24 or 30 FPS films to judder-free scenes when displayed in 50Hz/60Hz LCD panels. The SiS168 also includes a color management function of SiS Digital Native Video Engine technology (DNVETM), offering a flexibility to enhance the color performance on the converted picture frames.
SiS 168 is equipped with both the I2C bus, and SPI bus to easily adapt to HDTV system board or T-CON panel board, respectively. Besides, to accelerate the board-level EMI-compliance convergence, SiS168 supports the Spread Spectrum mechanism on the Quad-link LVDS bus and Dual-channel DDR2-1066 bus, respectively.
SiS 168 employs 0.11um 3.3V/1.2V silicon process, and is housed in a 484 LFBGA package. Engineer sample is available now for designing and validating and mass production is expected to start in May, 2009, SiS said.
