Fujitsu and Fraunhofer To Partner on Nanometre Technology
In exchanging expertise and granting mutual access to their IP pools, Fujitsu Semiconductor Europe and the Fraunhofer Institute for Integrated Circuits (IIS) are facilitating the development of future-proof nanometre chips for their customers.
As part of this co-operation, new research and development projects have been under way since the beginning of 2010. These are aimed at multimedia, image processing and navigation applications in the automotive, industrial and telecommunications markets.
For this purpose, Fujitsu is making available its analogue and digital nanometre technology libraries, IP (intellectual property) pool and expertise. Fraunhofer IIS is complementing this with its own IP and decades of experience in IC and system design. Chip designs, right up to the GDSII data, are developed and evaluated together with their customers. Fujitsu is producing prototypes in 90 nm and 65 nm CMOS technologies on multi-project wafers (MPW) at reduced mask costs.
"Industry, research and training all benefit from this co-operation. It grants cost-effective and dependable access to the latest nanometre technology for research projects, pilot series and products", comments Josef Sauerer, Head of IC Design at Fraunhofer IIS.
Mark Ellins, Director for ASIC and Foundry Services at Fujitsu Semiconductor Europe said "We are very pleased to be able to work together with such an experienced design partner as Fraunhofer IIS, and believe our co-operation will provide signficant benefits to developers requiring access to advanced process technologies".
For this purpose, Fujitsu is making available its analogue and digital nanometre technology libraries, IP (intellectual property) pool and expertise. Fraunhofer IIS is complementing this with its own IP and decades of experience in IC and system design. Chip designs, right up to the GDSII data, are developed and evaluated together with their customers. Fujitsu is producing prototypes in 90 nm and 65 nm CMOS technologies on multi-project wafers (MPW) at reduced mask costs.
"Industry, research and training all benefit from this co-operation. It grants cost-effective and dependable access to the latest nanometre technology for research projects, pilot series and products", comments Josef Sauerer, Head of IC Design at Fraunhofer IIS.
Mark Ellins, Director for ASIC and Foundry Services at Fujitsu Semiconductor Europe said "We are very pleased to be able to work together with such an experienced design partner as Fraunhofer IIS, and believe our co-operation will provide signficant benefits to developers requiring access to advanced process technologies".
