Cadence Tensilica DNA 100 Processor IP for On-Device AI
Cadence and Micron Prototype First DDR5 Memory
The DDR5 standard has not been finalized by JEDEC, but Cadence and micron have prototyped its first IP interface in silicon for a preliminary...
Imec and Cadence Tape Out First 3nm Chip
Imec and Cadence Design Systems are working toward a 3-nm tapeout of a 64-bit processor, aims to produce a working chip later this year...
Cadence Releases First PCI Express 5.0 Verification IP
Cadence has made availabile the first Verification IP (VIP) in support of the new PCI Express (PCIe) 5.0 architecture, driving early adoption of next-generation...