TSMC Reports Foundry's First 28 Nanometer Low Power Platform Technology with Fully Functional 64Mb SRAM
Taiwan Semiconductor Manufacturing Company today announced it has successfully developed the first 28-nanometer (nm) low power technology that continues the scaling trend and extends Silicon Oxynitride (SiON)/poly usage beyond 32 nanometer with a dual/triple gate oxide process.
Other characteristics from this technology includes high density and low Vcc_min 6-T SRAM cells, low leakage transistors, well-proven conventional analog/RF/electrical fuse components and low-RC Cu-low-k interconnect. This development was presented today in a paper at the 2009 Symposia on VLSI Technology and Circuits in Kyoto, Japan.
Additionally, the paper reports good 64Mb SRAM functional yield with a competitive cell size of 0.127 um², and a raw gate density as high as 3900 kGate/mm² in this 28nm dual/triple gate oxide SoC technology. Good SRAM Vcc_min, electrical fuse, and analog performance have also been achieved which proves the manufacturability of this technology.
In the paper presented, low standby and low operating power transistors using SiON optimized with strain engineering and aggressive oxide thickness provide up to 25~40% speed improvement or 30~50% active power reduction over prior 45nm technology.
"This development was achieved through close collaboration with customers who are pushing their own boundaries of new applications requiring 28nm technology," said Dr. Jack Sun, vice president R&D at TSMC.
In the previous announcement made in September 2008, TSMC plans to deliver its 28nm process in early 2010 as a full node technology offering options of power-efficient high performance and lower power technologies. TSMC is now on track to deliver 28nm technology platforms to its customers.
Additionally, the paper reports good 64Mb SRAM functional yield with a competitive cell size of 0.127 um², and a raw gate density as high as 3900 kGate/mm² in this 28nm dual/triple gate oxide SoC technology. Good SRAM Vcc_min, electrical fuse, and analog performance have also been achieved which proves the manufacturability of this technology.
In the paper presented, low standby and low operating power transistors using SiON optimized with strain engineering and aggressive oxide thickness provide up to 25~40% speed improvement or 30~50% active power reduction over prior 45nm technology.
"This development was achieved through close collaboration with customers who are pushing their own boundaries of new applications requiring 28nm technology," said Dr. Jack Sun, vice president R&D at TSMC.
In the previous announcement made in September 2008, TSMC plans to deliver its 28nm process in early 2010 as a full node technology offering options of power-efficient high performance and lower power technologies. TSMC is now on track to deliver 28nm technology platforms to its customers.
