Shipping in limited quantities since September, the TILE-Gx36 and TILE-Gx16 64-bit processors, fabricated in 40 nm, are now generally available. The Tile-GX36 chip will initially ship at clock speeds of 1.2GHz, and draws up to 24 watts of power.
The chips feature 36 identical processor cores (tiles) interconnected with Tilera's iMesh on-chip network. Each tile consists of a complete processor as well as L1 and L2 cache and a non-blocking switch that connects the tiles into the mesh. Each tile can independently run a full operating system, or multiple tiles taken together can run a multiprocessing OS like SMP Linux. The TILE-Gx family processor is also integrating a complete set of memory and I/O controllers, eliminating the need for an external north bridge or south bridge. TileDirect technology provides coherent I/O directly into the tile caches to deliver low-latency packet processing performance. Tilera's DDC (Dynamic Distributed Cache) system enables scalable performance for threaded and shared memory applications.
The TILE-Gx processors are programmed in ANSI standard C and C++. Tiles can be grouped in clusters to apply the appropriate amount of horsepower to each application. Since multiple, virtualized operating system instances can be run on the TILE-Gx simultaneously, it can replace multiple CPU and DSP subsystems for both the data plane and control plane.
In networking, a single TILE-Gx36 can deliver more than 40 gigabits per-second of L2/L3 packet forwarding performance across small and large packet sizes using less than 25 watts of power.
In cloud, a single TILE-Gx36-based server can provide better performance than an Intel Xeon-based system at one-fifth the power and one-eighth the space, according to Tilera.
The TILE-Gx36 has als odemonstrated a CoreMark score of over 165,000, while consuming a fraction of the power of the nearest competitor.
Generally, it' shard to make an apples-to-apples comparison as chip architectures have their own attributes. Low-power processors from ARM and Tilera could be beneficial for fast-moving cloud transactions, while the dominant x86 chips are proven and can handle resource-heavy applications like databases.
Tilera chips are already being tested in some servers, and early adopters Hewlett-Packard and chip maker Nvidia are building experimental servers with low-power ARM processors, which are found in most smartphones and tablets today. Tilera, ARM and x86 chips are based on separate instruction sets.
Rival architectures like ARM and MIPS have their benefits on power consumption, but the total cost of ownership needs to be considered before comparing architectures.
With Intel's Xeon, there is almost unlimited software support and low total cost of ownership. There is also an alternate chip company in AMD, which is competitive in both price and performance.
Tilera is also offering evaluation systems in multiple form-factors, scaling from compact size PCIe cards to high performance appliances. The Tilera PCIe cards offer the first 36-core PCIe half-size card. The full featured appliance scales from a single 36-core TILE-Gx processor to a four processor 1U appliance with a total of 144 cores per 1U box. Additional boards and systems from our partners will be announced later in the year.
In related news, Tilera also today welcomed back Tilera co-founder Devesh Garg, 46, as Tilera's CEO. Garg served as the company's CEO from its inception in 2004 until October 2007. Garg was a Managing Director in the Bessemer Venture Partners India fund for the past three years, but has remained active in the company as an investor and shareholder. He will be based at Tilera?s headquarters in San Jose, Calif.