Samsung's paper also described a new technique that appears to be a small but significant advance on past efforts.
According to Samsung, the design sports an "integrated assist circuitry that improves the minimum voltage levels (Vmin) for the high density version and HC bitcells by 130mV and 80mV, respectively. This dual-transient word-line technique also lowered minimum voltage levels for the 10nm SRAM to 45 mV for a high-current part.
This technique was essential as the 10nm SRAM is so small it has unattractive minimum voltage levels due to the effects of process variations.
Samsung said that the 10nm fin improves performance, although the back-end resistance does not improve compared to 14nm. The company said that unlike rival TSMC which puts finFETs on its 20nm interconnects to create its 16nm process, Samsung’s 14nm process uses the same design rules for its interconnects and finFETs. It will continue the practice at 10nm, however the company would not give the exact measure of the finest lines used in either process.
Samsung indicated that the 10nm node will offer similar performance increases to the 14nm process.
The S. Korean company has taped out test chips in its second-generation finFET process but not products yet.
Samsung's presentation left everyone with some questions. The company did not disclose the exact benefits that the 10nm process will offer in terms of lower power consumption or higher speeds or whether logic circuits would get the same 38% shrink as SRAM.