The specification extends the data rate to 5GT/s in a manner compatible with all existing PCIe 1.1 products currently supporting 2.5GT/s signaling. The key benefit of PCIe 2.0 is its faster signaling, effectively increasing the aggregate bandwidth of a 16-lane link to approximately 16 GB/s. The higher bandwidth will allow product designers to implement narrower interconnect links to achieve high performance while reducing cost.
In addition to the faster signaling rate, PCI-SIG working groups also added several new protocol layer improvements to the PCIe Base 2.0 specification. These architecture improvements include:
- Dynamic link speed management allows developers to control the speed at which the link is operating
- Link bandwidth notification alerts platform software (operating system, device drivers, etc) of changes in link speed and width
- Capability structure expansion increases control registers to better manage devices, slots and the interconnect
- Access control services allows for optional controls to manage peer-to-peer transactions
- Completion timeout control allows developers to define a required disable mechanism for transaction timeouts
- Function-level reset provides an optional mechanism to reset functions within a multi-function device
- Power limit redefinition enables slot power limit values to accommodate devices that consume higher power
The PCIe Base 2.0 specification is available for download at http://www.pcisig.com/specifications/pciexpress/base2/.