Sony, Toshiba, NEC Electronics Develop 45nm Chip Platform
Sony, Toshiba and NEC Electronics Corp., said on Thursday they
had jointly developed technology to mass produce cutting-edge
chips.
The platform developed by the three Japanese companies will be
used to make system chips, which combine multiple functions on a
sliver of silicon, using 45-nanometre technology, the firms said
in a joint press release. This technology was unveiled on
December 13 (US Pacific Standard Time) at Session 27.2 of the
2006 International Electron Devices Meeting (IEDM) in San
Francisco, CA.
Chip makers worldwide are locked in a race to lower production costs on 90-, 65- and 45-nanometre chips, with the smaller circuitry widths allowing more power per chip for complex devices.
The three companies are developing a platform for low-power system chips, to be completed in early 2007.
Toshiba and NEC Electronics are also working to standardize technology to make advanced chips with circuitry width of 45-nanometres or finer with Fujitsu and Renesas Technology Corp.
The key elements of the new platform are a fully renovated MOSFET integration scheme, and a hybrid structure with a low dielectric constant (low-k) film that assures high performance and reliability.
The MOSFET integration process applies strained silicon technology to the transistor, utilizing crystal lattice distortion to induce performance-boosting local strain at key locations. Optimization of the strain boosts transistor performance to a level 30% faster than that achieved in the present generation of technology.
Application of a low-k film in the intermediate metal layer of the chip during the back-end process reduces parasitic capacitance and improves circuit performance. The three partners confirmed a dielectric gate film with an effective 15-year lifetime, a span surpassing the average lifetime of a high performance LSI. They also carried out tests of the platform and proved a layer yield of over 98% for the challenging back-end process, confirming that the technology achieves the reliability essential for mass production.
In addition, the partners have led the industry in applying immersion lithography technology with an ultra-high numerical aperture (NA) of over 1.0 to formation of the transistor node, achieving a cell with an area of 0.248 micron m2 in an ultra high density SRAM. The new cell is the smallest yet achieved.
The three companies are simultaneously developing two 45nm processes -- the current platform, which is ideal for high performance LSIs, as well as a platform for applications with low power consumption requirements, which is expected to be completed in early 2007.
Chip makers worldwide are locked in a race to lower production costs on 90-, 65- and 45-nanometre chips, with the smaller circuitry widths allowing more power per chip for complex devices.
The three companies are developing a platform for low-power system chips, to be completed in early 2007.
Toshiba and NEC Electronics are also working to standardize technology to make advanced chips with circuitry width of 45-nanometres or finer with Fujitsu and Renesas Technology Corp.
The key elements of the new platform are a fully renovated MOSFET integration scheme, and a hybrid structure with a low dielectric constant (low-k) film that assures high performance and reliability.
The MOSFET integration process applies strained silicon technology to the transistor, utilizing crystal lattice distortion to induce performance-boosting local strain at key locations. Optimization of the strain boosts transistor performance to a level 30% faster than that achieved in the present generation of technology.
Application of a low-k film in the intermediate metal layer of the chip during the back-end process reduces parasitic capacitance and improves circuit performance. The three partners confirmed a dielectric gate film with an effective 15-year lifetime, a span surpassing the average lifetime of a high performance LSI. They also carried out tests of the platform and proved a layer yield of over 98% for the challenging back-end process, confirming that the technology achieves the reliability essential for mass production.
In addition, the partners have led the industry in applying immersion lithography technology with an ultra-high numerical aperture (NA) of over 1.0 to formation of the transistor node, achieving a cell with an area of 0.248 micron m2 in an ultra high density SRAM. The new cell is the smallest yet achieved.
The three companies are simultaneously developing two 45nm processes -- the current platform, which is ideal for high performance LSIs, as well as a platform for applications with low power consumption requirements, which is expected to be completed in early 2007.
