The performance of the new core was boosted by increasing the number of instruction execution pipeline stages to nine, from five in Toshiba's previous processor core. The new core is also optimized for design of high-performance customized processors by integration of a reorder buffer circuit that manages and shortens waiting cycles for user extension instructions. The present implementation of the core was manufactured with 65nanometer (nm) process technology, and that too contributed to achieving the 1GHz clock speed. The new configurable processor core is designed with register transfer level description (RTL) and can be manufactured with other process technology, including 90nm technology.
The details of the processor and its technology were announced today (August 16, local time) at HOT CHIPS17, the international processor conference that opened at Stanford University on August 14.
The market for digital equipment supporting images, audio and communications is growing fast. However, the required performance and type of data processing in system LSI differs by application, and the overall volume of handled data is rapidly increasing. As a result, there is growing demand for customizable high-performance embedded processors. Toshiba will continue to develop MeP technology and to apply high-end gigaherz-level MeP cores to SoC for digital products.
Outline of MeP:
MeP is a configurable processor that allows designers to customize processor configurations, including custom instructions and embedded memory capacity, in about 1 million different combinations. The processor features small chip size, low power consumption and high-speed processing. It is based on a 32-bit RISC processor, appropriate for digital media products that require processing of large volume of image and audio data, such as digital TVs and DVD recorders.
MeP main features:
1. High-speed media processing (image and audio) 2. Customizable configuration, including embedded-memory capacity 3. Extensibility of hardware allowing easy addition of functions
These features contribute to shorter development times for SoC that integrate complicated functions, reducing the development time for digital products.
Toshiba uses MeP in its own products and also licenses the technology to third parties that require flexibility in circuit design. Users who want to apply MeP to their own products can download MeP design data and related information from Toshiba's dedicated website, http://www.MePcore.com/, after registration and completing a license agreement.
Roadmap of MeP:
Toshiba developed its first MeP core, MeP-c1 which had a 5-stage pipeline structure in 2001. Toshiba expanded MeP functionality, creating its line of c-series products, with the MeP-c2 and MeP-c3. The new core announced today, MeP-h1, introduces a 9-stage pipeline structure as the first core in the new high-performance h series. Toshiba is also developing MeP-c4, an enhanced c-series core