Synopsys, Inc. today announced the new DesignWare ARC HS5x and HS6x processor IP families for high-performance embedded applications.
The 32-bit ARC HS5x and 64-bit HS6x processors, available in single-core and multicore versions, are implementations of a new superscalar ARCv3 Instruction Set Architecture (ISA) and deliver up to 8750 DMIPS per core in 16-nm process technologies under typical conditions, making them the highest performance ARC processors to date.
The multicore versions of the new ARC HS processors include an interconnect fabric that links up to 12 cores and supports interfaces for up to 16 hardware accelerators, all while maintaining coherency among the cores. The processors can be configured for real-time operation or with a memory management unit (MMU) that supports symmetric multiprocessing (SMP) Linux and other high-end operating systems. To accelerate software development, the ARC HS5x and HS6x processors are supported by the ARC MetaWare Development Toolkit that generates efficient code. The new ARC HS processors are designed to meet the power, performance, and area requirements of a broad range of high-end embedded applications including solid-state drives (SSDs), automotive control & infotainment, wireless baseband, wireless control, and home networking.
The ARC HS5x and ARC HS6x processors are based on the new ARCv3 ISA that implements a full range of 32-bit and 64-bit instructions. These processors feature a high-speed 10-stage, dual-issue pipeline that offers increased utilization of functional units with a limited increase in power and area. The HS5x processors feature a 32-bit pipeline that can execute all ARCv3 32-bit instructions, while the HS6x processors feature a full 64-bit pipeline and register file that can execute both 32-bit and 64-bit instructions. In addition, the ARC HS6x supports 64-bit virtual and 52-bit physical address spaces to enable direct addressing of current and future large memories, as well as 128-bit loads and stores for efficient data movement. Multicore versions of both the ARC HS5x and HS6x processors include a high-bandwidth intra-processor interconnect that has been designed to ease development and timing closure with asynchronous clocking and up to 800 GB/s internal aggregate bandwidth. To further simplify physical design and timing closure in multicore configurations, each core can reside in its own power domain and have an asynchronous clock relationship with the other cores.
A new 128-bit vector floating point unit supports F16, F32, and F64 operations with a 2-cycle accumulation latency. Like all ARC processors, the HS5x and HS6x processors are configurable and implement ARC Processor EXtension (APEX) technology that enables the support of custom instructions to meet the performance, power, and area requirements of each target application.
The HS5x and HS6x processors are supported by Synopsys' ARC MetaWare Development Toolkit that includes a C/C++ compiler optimized for the processors' superscalar architecture, a multicore debugger to debug and profile code and a fast instruction set simulator (ISS) for pre-hardware software development. A cycle-accurate simulator is also available for design optimization and verification. Open-source software support for the processors includes the Zephyr real-time operating system, an optimized Linux kernel, the GNU Compiler Collection (GCC), GNU Debugger (GDB), and the associated GNU programming utilities (binutils).
The DesignWare ARC HS5x and HS6x processors are scheduled to be available in Q3, 2020. The new processors will include the ARC HS56, HS57D, HS58, HS66, HS68 and multicore versions (HS56MP, HS57DMP, HS58MP, HS66MP, HS68MP) of each.