ARM Artisan physical IP for Samsung's 14nm FinFET process technology is now available for SoC designers.
Through collaboration with Cadence, Samsung offers a full RTL-to-signoff flow optimized for the 14nm FinFET process. This flow has been used to implement multiple early tapeouts on the process, including the first announced ARM processor tapeout in December 2012. Cadence provides a complete methodology for custom and digital design, place-and-route, extraction, timing, physical verification and DFM, including support for the Cadence Virtuoso and Encounter platforms through SKILL-based PDKs, EDI System and QRC extraction tech files and Physical Verification System rule decks.
Mentor is supporting Samsung's 14nm FinFET process technology with its Manufacturing Analysis and Scoring (MAS) deck, which prioritizes different DFM effects and makes recommendations on how to modify the design. Sign-off enabling for 14nm FinFET process technology also includes decks for design rule checking with double patterning and pattern matching-based verification, layout vs. schematic checking, lithography friendly design, and DFM with advanced fill.
The entire Synopsys Galaxy Design Platform is broadly supported on Samsung's 14nm FinFET process, for design tasks ranging from custom design through final place-and-route and signoff of complex SoCs. The Galaxy Design Platform tools, Samsung Foundry 14nm FinFET PDKs and associated tool usage have been tuned to deliver optimal results for SoC designers targeting the power and performance benefits of FinFET technology. Synopsys and Samsung have also proven the process, tool capabilities and IP in silicon via a series of complex SoCs which included both high performance processors and Synopsys-developed IP, including the recently certified DesignWare USB 3.0 femtoPHY.
With process design kit of 14nm FinFET process technology available today, Samsung's customers can start designing with silicon-based SPICE models, extraction decks, design rule manuals and technology files that have been developed based on silicon results from 14nm FinFET test chips run in Samsung?s 300mm fabs.
The PDK includes router tech files and other design enablement features to support the new 3-dimensional FinFET device structures, middle of line (MOL), and double patterning enablement used in the back end of line (BEOL) process.