NVM Express Specification Released for PCIe-based SSDs
The NVMHCI Work Group has released the NVM Express 1.0 specification that will allow the industry to create PCI Express (PCIe)-based Solid-State Drives (SSDs).
The new specifications will improve the performance of SSDs operating on
multi-core architectures, as well as improve time to market.
Intel, along with 70 NVMHCI members, collaborated on the spec. Implementation of the NVM Express (i.e., Non-Volatile Memory Host Controller Interface Specification) requires a license from Intel.
NVM Express defines an optimized register interface, command set, and feature set for high performance PCI Express based Solid-State Drives (SSDs). This specification is intended for hardware component designers, system builders and device driver (software) developers.
The interface includes several key features for scalability. A device may support up to 64K I/O queues with up to 64K commands per queue. The interrupt architecture supports MSI-X and interrupt aggregation. The interface efficiently supports multi-core by ensuring thread(s) may run on each core with its own queue & interrupt without any locks required. For Enterprise class solutions, there is support for end-to-end data protection, security & encryption capabilities, as well as robust error reporting and management capabilities.
There are numerous benefits to a standard interface through the interoperability it fosters. Each OS vendor may confidently write a driver that works for devices from multiple vendors. OEMs may procure devices from diverse suppliers that all implement a consistent feature set.
Intel, along with 70 NVMHCI members, collaborated on the spec. Implementation of the NVM Express (i.e., Non-Volatile Memory Host Controller Interface Specification) requires a license from Intel.
NVM Express defines an optimized register interface, command set, and feature set for high performance PCI Express based Solid-State Drives (SSDs). This specification is intended for hardware component designers, system builders and device driver (software) developers.
The interface includes several key features for scalability. A device may support up to 64K I/O queues with up to 64K commands per queue. The interrupt architecture supports MSI-X and interrupt aggregation. The interface efficiently supports multi-core by ensuring thread(s) may run on each core with its own queue & interrupt without any locks required. For Enterprise class solutions, there is support for end-to-end data protection, security & encryption capabilities, as well as robust error reporting and management capabilities.
There are numerous benefits to a standard interface through the interoperability it fosters. Each OS vendor may confidently write a driver that works for devices from multiple vendors. OEMs may procure devices from diverse suppliers that all implement a consistent feature set.
