Xilinx is lifting the veil on its next-generation Versal Premium offering that will deliver significantly higher throughput and logic density, along with integrated Ethernet, Interlaken scalable, chip-to-chip interconnect technology, and cryptographic engines for enabling high-performance and secure networks.

Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.

Versal is the first adaptive compute acceleration platform (ACAP), a new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC's 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to-market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast networks.

"The Versal Premium series takes ACAPs to the next level delivering breakthrough networked hard IP integration enabling the development of single chip 400G and 800G solutions," said Kirk Saban, vice president of Product and Platform Marketing at Xilinx. "Targeting next-generation networks and cloud deployments, Versal Premium delivers superior bandwidth and compute density in a scalable platform that is readily programmable by hardware and software developers alike for optimized acceleration and reduced TCO."

The Versal Premium series is built on a foundation of the currently shipping Versal AI Core and Versal Prime ACAP series. New to Versal Premium are 112Gbps PAM4 transceivers, multi-hundred gigabit Ethernet and Interlaken connectivity, high-speed cryptography, and PCIe Gen5 with built-in DMA, supporting both CCIX and CXL.

The Versal Premium series is delivering up to 9Tb/s of scalable, adaptable serial bandwidth. This is achieved by utilizing 112G PAM4 transceivers and integrated connectivity for core, metro and data center interconnect (DCI) infrastructure that doubles bandwidth density per port and reduce latency by up to 50 percent.

The pre-engineered connectivity enables secure, multi-terabit Ethernet with the flexibility to support a variety of data rates and protocols. Channelized Ethernet cores deliver up to 5Tb/s of throughput in a minimized footprint and high-speed cryptography engines provide up to 1.6Tb/s of encrypted line-rate throughput and support for AES-GCM-256/128, MACsec, and IPsec.

The over 120TB/s of on-chip memory bandwidth, coupled with the customizable memory hierarchy, reduces data movement to remove key bottlenecks, while pre-engineered connectivity and cores allow drop-in integration into existing cloud infrastructure.

Xilinx says the Versal Premium series will begin sampling with early access customers in the first half of 2021, but documentation is available now and customers can start prototyping with the existing Versal Prime Evaluation Kit.