Toshiba to Develop 16-Gigabit NAND Flash Memory with 43nm Process Technology
Toshiba today announced development of technology for a 16-gigabit (Gb) NAND flash memory chip fabricated with 43-nanometer (nm) process technology co-developed with SanDisk.
The technology of the new chip was reported on February 6, in Session 23.6 of the International Solid-State Circuits Conference (ISSCC) 2008 in San Francisco.
The new 16Gb products have a chip area of approximately 120 square millimeters, about 30 percent less than the same-density NAND flash memories jointly developed by Toshiba and SanDisk and fabricated with 56nm process technology. Memory cells are grouped and controlled in NAND strings of 64 cells aligned in parallel, double the number of 56nm devices, with a dummy word-line cell at either end to prevent program disturbance. This technology contributes to reduce the number of select gates and to improve memory area efficiency. Modification of the peripheral circuit design also contributes to reduced chip area: the addition of high voltage switches to the circuit reduces the number of control-gate driver circuits required to drive word lines, and ground buses are routed on the memory cell arrays.
Toshiba will start shipments of commercial samples of new 16Gb (2 gigabyte) single-chip, multi-level cell (MLC) NAND flash memories, the current mainstream density, from today and start mass production from March. The company intends to start mass production of 32Gb (4 gigabyte) NAND flash memories early in the third quarter of this year (JulySeptember 2008). The new chips will be produced at Fab 4, the latest 300mm wafer fabrication facility at Toshiba's Yokkaichi Operations, in Mie prefecture, Japan.
The new 16Gb products have a chip area of approximately 120 square millimeters, about 30 percent less than the same-density NAND flash memories jointly developed by Toshiba and SanDisk and fabricated with 56nm process technology. Memory cells are grouped and controlled in NAND strings of 64 cells aligned in parallel, double the number of 56nm devices, with a dummy word-line cell at either end to prevent program disturbance. This technology contributes to reduce the number of select gates and to improve memory area efficiency. Modification of the peripheral circuit design also contributes to reduced chip area: the addition of high voltage switches to the circuit reduces the number of control-gate driver circuits required to drive word lines, and ground buses are routed on the memory cell arrays.
Toshiba will start shipments of commercial samples of new 16Gb (2 gigabyte) single-chip, multi-level cell (MLC) NAND flash memories, the current mainstream density, from today and start mass production from March. The company intends to start mass production of 32Gb (4 gigabyte) NAND flash memories early in the third quarter of this year (JulySeptember 2008). The new chips will be produced at Fab 4, the latest 300mm wafer fabrication facility at Toshiba's Yokkaichi Operations, in Mie prefecture, Japan.
