JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of JESD317: Compute Express Link (CXL™) Memory Module Base Standard, known as “CMM”. JESD317 CMM defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL™-attached memory modules, and is available for free download from the JEDEC website.

CMM is designed to provide reference base targets for CXLTM-attached memory modules to help simplify system design and minimize industry confusion for first adoption. By leveraging established industry standard specifications from SNIA (EDSFF), PCIe, and CXLTM to define specific module implementations, CMM enables system providers to accommodate certain known devices while leaving room for innovation. The standard also supports system device slots designed to be compatible with both CMMs and traditional PCIe-attached NVMe drives. For a deeper dive, catch JEDEC’s session at FMS 2023 in Santa Clara, CA, on Wednesday, August 9th at 8:30AM: Breaking Past Expansion Limits: CXL-Attached Memory Standards.

“The high-speed memory capabilities offered by CXLTM memory modules are increasingly important to the industry and critical to many emerging applications such as artificial intelligence and data analytics,” said Mian Quddus, JEDEC Board of Directors Chairman. He added: “JEDEC’s goal with the development of JESD317 CMM is to offer suppliers of CXLTM -attached memory industry-aligned targets to support broader adoption.”

“JEDEC’s new CMM standard establishes a first common starting point for CXLTM memory expansion and lowers the barrier of technology adoption for both suppliers and system manufacturers,” noted Jonathan Hinkle, Chair of JEDEC’s CXL Memory Task Group. He added: “In a dedicated effort underscoring the importance of this standard for the industry, key companies joined forces in the TG to align and drive this first standard, including major hyperscale and enterprise system designers, memory suppliers, and processor vendors.”