The new HMCC 2.0 interface specification for Hybrid Memory Cube (HMC) technology advances data rate speeds from 15 Gb/s up to 30 Gb/s, establishing a new threshold for memory performance. Released today by the Hybrid Memory Cube Consortium (HMCC), HMCC 2.0 also migrates the associated channel model from short reach (SR) to very short reach (VSR) to align with existing industry nomenclature.

The HMCC was founded in October 2011 by co-developers Altera, Micron, Open-Silicon, Samsung Electronics and Xilinx. The HMCC finalized and released its first specification in May 2013. Since its establishment, the HMCC has grown to include more than 150 OEMs.

HMC has been designed to address the limitations imposed by conventional memory technology by providing high system performance with significantly lower power per bit. The current generation of HMC technology delivers up to 15 times the bandwidth of a DDR3 module and uses 70 percent less energy and 90 percent less space than such technologies. HMC's memory manages error correction, resiliency, refresh and other parameters exacerbated by memory process variations.