Toshiba Develops Circuit Techniques for Power-efficient Embedded SRAM
Toshiba has developed circuit techniques for embedded SRAM that operate in a wide supply voltage range, from 0.5V to 1.0V, which effectively contribute to lower power consumption of electronic devices.
The test chip fabricated employs three new techniques to ensure proper operation of SRAM even when the operating voltage varies. At the same time, cell failure rate is reduced and fast operation is achieved. Toshiba has demonstrated these techniques in a 40nm 2Mb SRAM test chip at 0.5V operation. This achievement was reported today at the IEEE Asian Solid-State Circuits Conference (A-SSCC) 2011, now being held in South Korea.
The chip employs three new techniques to achieve stable operation even when the voltage varies or is low.
Embedded SRAM in LSI for mobile equipment have multiple cells for data storage and must achieve stable performance even if cell characteristics vary. Conventional SRAM techniques employ wordline selection signals for read/write operations. As operating conditions, such as transistor thresholds, temperature and voltage, vary, the optimum wordline voltage at which SRAM cells properly operate also changes. Toshiba's new circuit technique predicts SRAM cell failure rate in real time and automatically programs wordline voltage so that the cell memory is retained even when operating conditions vary. The result is a reduction in the cell failure rate to one-hundredth that of conventional SRAM. This new circuit technique also eliminates the need to program the wordline level voltage chip by chip, which conventional SRAM require.
When sense amplifier activation timing is adjusted to the slowest cell in low-voltage operation, it becomes too slow in high-voltage operation and SRAM performance slows. The new technique controls wordline voltage so that the voltage characteristics of the control circuit, which determines the sense amplifier activation timing, match the slowest cell's voltage characteristics. Consequently, activation at the optimum timing is possible at any operating voltage. This technique improves the activation timing in high-voltage operation even if the sense amplifier activation timing is optimized at the lowest operating voltage, resulting in an 18% improvement in operating frequency.
Another issue is an increased malfunction rate for SRAM cells affected by bit lines in read/write operations at low voltage, such as below 0.7V. Whereas the conventional technique selects wordlines one by one, the new technique simultaneously activates eight wordlines to read/write the same data, achieving operation at voltage as low as 0.5V, although available memory capacity is reduced.
These three new techniques realize embedded SRAM capable of operating in a wide voltage range. Power consumption at 0.5V operation is 57% less than that of conventional SRAM.
The chip employs three new techniques to achieve stable operation even when the voltage varies or is low.
Embedded SRAM in LSI for mobile equipment have multiple cells for data storage and must achieve stable performance even if cell characteristics vary. Conventional SRAM techniques employ wordline selection signals for read/write operations. As operating conditions, such as transistor thresholds, temperature and voltage, vary, the optimum wordline voltage at which SRAM cells properly operate also changes. Toshiba's new circuit technique predicts SRAM cell failure rate in real time and automatically programs wordline voltage so that the cell memory is retained even when operating conditions vary. The result is a reduction in the cell failure rate to one-hundredth that of conventional SRAM. This new circuit technique also eliminates the need to program the wordline level voltage chip by chip, which conventional SRAM require.
When sense amplifier activation timing is adjusted to the slowest cell in low-voltage operation, it becomes too slow in high-voltage operation and SRAM performance slows. The new technique controls wordline voltage so that the voltage characteristics of the control circuit, which determines the sense amplifier activation timing, match the slowest cell's voltage characteristics. Consequently, activation at the optimum timing is possible at any operating voltage. This technique improves the activation timing in high-voltage operation even if the sense amplifier activation timing is optimized at the lowest operating voltage, resulting in an 18% improvement in operating frequency.
Another issue is an increased malfunction rate for SRAM cells affected by bit lines in read/write operations at low voltage, such as below 0.7V. Whereas the conventional technique selects wordlines one by one, the new technique simultaneously activates eight wordlines to read/write the same data, achieving operation at voltage as low as 0.5V, although available memory capacity is reduced.
These three new techniques realize embedded SRAM capable of operating in a wide voltage range. Power consumption at 0.5V operation is 57% less than that of conventional SRAM.
