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Thursday, December 28, 2017
Samsung to Develop Its Own Fo-WLP Chip Packaging Process

Samsung Electronics will reportedy develop its own semiconductor packaging process in 2018, as the company is trying to win back foundry orders for Apple's application processors (AP) that were taken by TSMC in 2016.

South Korean ETNews reports that Samsung Electronics Semiconductor Business Department is making investments in order to develop the new Fanout-Wafer Level Package (Fo-WLP) process. Samsung Electronics' goal is to establish a mass-production system for the new process by 2019.

In short, packaging protects the chip (die) when it is cut from a silicon wafer. The process protects the chip from moisture, impurities, and impact and delivers signals to the main PCB. A goal is to make the chip's area small in order to be able to add more I/O (Input/Output) terminals.

Fan-out technology pulls the wiring outside the chip, allowing for thinner ovearall packaging and lower production costs. Specificaly, the FoWLP technology is an enhancement of standard wafer-level packages (WLPs) developed to provide a solution for semiconductor devices requiring a higher integration level and a greater number of external contacts. It provides a smaller package footprint with higher input/output (I/O) along with improved thermal and electrical performance.

In conventional WLP schemes I/O terminals are located over the chip surface area. Using this method, there is a limitation to the number of I/O connections.

FOWLP takes individual die and embeds them in a low cost material such as epoxy mold compound (EMC) with space allocated between each die for additional I/O connection points - avoiding the use of relatively expensive Si real estate to accommodate a high I/O count. Redistribution Layers (RDL) are formed using PVD seed deposition and subsequent electroplating/patterning to re-route I/O connections on the die to the mold compound regions in the periphery.

TSMC was the first in the world to commercialize the Fo-WLP technology for APs and it was able to win orders for the 16nm A10s chips for the iPhone 7 and the 10nm A11s for the iPhone 8. TSMC calls its packaging process Fo-WLP.

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