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Tuesday, November 28, 2017
Western Digital to Bring RISC-V Processors into Drives, AI

Western Digital announced that it will standardize on RISC-V processors and has invested in Esperanto Technologies, a startup designing high-end SoCs and cores using the open-source instruction set architecture.

WD expects that it could ship as many as 2 billion RISC-V chips a year inside its hard-disk and solid-state drives. The company also revealed that it is working on machine-learning accelerators for inference.

In his keynote address, Western Digital's Chief Technology Officer Martin Fink expressed the company's commitment to help lead the advancement of data-centric compute environments through the work of the RISC-V Foundation. RISC-V is an open and scalable compute architecture that will enable the diversity of Big Data and Fast Data applications and workloads proliferating in core cloud data centers and in remote and mobile systems at the edge.

"RISC-V will allow the entire industry to realize the benefits of next-generation architectures while also enabling us to create more purpose-built devices, platforms and storage systems for Big Data and Fast Data applications. We are moving beyond just storing data to now creating entire environments that will enable users to realize the value and possibilities of their data," said Mike Cordano, president and chief operating officer, Western Digital.

To contribute toward the advancement and success of the RISC-V ecosystem, Western Digital plans to transition future core, processor, and controller development to the RISC-V architecture. The company currently consumes over one billion processor cores on an annual basis across its product portfolio. The transition will occur gradually and once completely transitioned, Western Digital expects to be shipping two billion RISC-V cores annually. The company is committed to advancing RISC-V technology for use in mission-critical applications so that it can be deployed in its products.

Western Digital is engaged in active partnerships and investments in RISC-V ecosystem partners. The company recently completed a strategic investment in Esperanto Technologies, a developer of high-performance, energy-efficient computing solutions based on the open RISC-V architecture. Esperanto, which is headquartered in Mountain View, Calif., includes a seasoned team of experienced processor and software engineers with the goal of making RISC-V the architecture of choice for compute-intensive applications, such as machine learning.

"The open source movement has demonstrated to the world that innovation is maximized with a large community working toward a common goal," said Fink. "For that reason, we are providing all of our RISC-V logic work to the community. We also encourage open collaboration among all industry participants, including our customers and partners, to help amplify and accelerate our efforts. Together we can drive data-focused innovation and ensure that RISC-V becomes the next Linux success story."

Esperanto tipped plans for a family of 64-bit RISC-V chips that will include:

  • An AI "supercomputer-on-a-chip" to be made in TSMC's 7-nm process.
  • A 16-core "ET-Maxion" targeting highest single-thread performance
  • A 4,096-core "ET-Minion" targeting performance-per-watt with a vector floating-point unit in each core.

How RISC-V Works

Comprising the machine language and I/O model of a computer or computing system, the ISA literally defines everything that a programmer needs to know in order to program it. RISC-V is an open ISA based on established reduced instruction set computing (RISC) principles. Its attribute set enables lower cycles per instruction (CPI) than a complex instruction set computer (CISC) architecture, mostly because it's based on a small set of simple and general instructions, versus a large set of complex and specialized ones, targeted at OS and application processing.

Because of its open, modular approach, RISC-V is suited to serve as the foundation of data-centric compute architectures, according to WD. As an OS processor, it can enable purpose-built architectures by supporting the independent scaling of resources. Its modular design approach allows for more efficient processors for edge and mobile systems.

Additionally, RISC-V can be freely used for any purpose - anyone can design, manufacture, and sell RISC-V chips and software. RISC-V and any CPU core designs are freely available under a Berkeley Software Distribution (BSD) license.

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