Samsung has shared more details about its next-generation Exynos 5 Dual dual-core mobile processor, which will be two times faster than comparable Exynos chips currently used in the company's smartphones and tablets.
The chip will also consume 30 percent less power than existing Exynos chips, the company said. The Exynos 5 Dual will have ARM's latest Cortex-A15 processor core running at 1.7GHz, while existing Exynos chips are based on the older ARM Cortex-A9 processor design.
Samsung's Exynos chips are used in a range of Galaxy smartphones and tablets. The Galaxy Note 10.1 tablet, due to become available later this month, will come with a quad-core version of the Exynos 4 chip.
The 32nm Exynos 5 Dual chip will have better multimedia performance than its predecessors, allowing mobile devices to display images at a 2560 by 1600-pixel (WQXGA) resolution, the company said. It can help devices play back full 1080p high-definition at 60 frames per second, double the normal rate. The Exynos 5 chip employs an ARM Mali T604 graphics processor with four cores, along with a 12.8GB/s memory bandwidth with 2-port 800MHz LPDDR3 for heavy traffic operations.
Other features include 3D graphics hardware, Image Signal Processor, and high-speed interfaces such as USB 3.0 and SATA3.
The 3D graphics performance is supported by a variety of APIs, such as openGL ES 2.0 and Halti, which can be used for GPUs with openCL full profile.
For the first time in the mobile industry, Exynos 5 Dual integrates eDP controller and PHY transceiver to save power, space and bill of materials (BOM). Integrated eDP is specially designed with low-power circuit and features hardwired logic to support Panel-Self-Refresh (PSR) protocol.
The chip's Image Signal Processor (ISP) of 8M pixel 30fps comes with addon post processing units, such as 3-Dimensional Noise Reduction (3DNR), Video Dgital Image Stabilization (VDIS), and Optical Distortion Compensation (ODC) integrated. Its ISP pipeline supports zero-shutter lag.
The chip also offers BOM savings by integrating USB Host/Dev3.0, HSIC with PHY transceivers, and eight channels of I2C supporting a variety of sensors.