Thursday, July 02, 2015
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
ARCHOS Unveils the ARCHOS 50d Helium
July 29 Won't Be The Day You Get Your Windoiws 10 Upgrade
Windows 7 Remains The Leading Operating System
Intel President To Leave The Company
Intel Compute Stick Comes With Ubuntu
Nintendo Wants To Surpise With New NX Console
South Korean Display Makers To Provide Flexible Display For Next Apple Watch: analyst
Hewlett-Packard Officially Files to Split
Active Discussions
How to back up a PS2 DL game
Copy a protected DVD?
roxio issues with xp pro
How to burn a backup copy of The Frozen Throne
Help make DVDInfoPro better with dvdinfomantis!!!
Copied dvd's say blank in computer only
menu making
Optiarc AD-7260S review
 Home > News > General Computing > Toshiba...
Last 7 Days News : SU MO TU WE TH FR SA All News

Monday, February 09, 2009
Toshiba Develops Highest Density Non-volatile RAM


Toshiba today announced the prototype of a new FeRAM ?Ferroelectric Random Access Memory? that redefines industry benchmarks for density and operating speed.

The new chip realizes storage of 128-megabits and read and write speeds of 1.6-gigabytes a second, the most advanced combination of performance and density yet achieved. Full details of the new FeRAM will be presented this week at the International Solid-State Circuits Conference 2009 (ISSCC2009) in San Francisco, USA.

The new FeRAM modifies Toshiba's original chainFeRAM architecture, which contributes to chip scaling, with a new architecture that prevents cell signal degradation, the usual tradeoff from chip scaling. The combination realizes an upscaled FeRAM with a density of 128-megabit. Furthermore, a new circuit that predicts and controls the fluctuations of power supply supports high-speed data transfers. This allowed integration of DDR2 interface to maximize data transfers at a high throughput at low power consumption, realizing read and write speeds of 1.6 gigabytes a second. In developing the new FeRAM, Toshiba broke its own record of 32-megabit density and 200-megabit data transfers, pushing performance to eight times faster than the transfer rate and density of the previous records and the fastest speed of any non-volatile RAM.

FeRAM combines the fast operating characteristics of DRAM with flash memory's ability to retain data while powered off, attributes that continue to attract the attention of the semiconductor industry. Toshiba said that it would continue R&D in FeRAM, aiming for further capacity increases and eventual use in a wide range of applications, including the main memory of mobile phones, mobile consumer products, and cache memory applications in products such as mobile PCs and SSDs.

In the earlier generation of 64-megabit FeRAM employed a data-line design in which neighboring data-lines operated in sequence: one is off when the other is on. This allowed off lines to provide a noise barrier between on lines, contributing to chip scaling and fine performance. Previous chain architecture collected four data-lines but Toshiba has successfully increased the number of data-lines to eight, which led to a decrease in the total chip area.

Chip scaling causes signal degradation as the stored polarization of memory cell gets smaller. By shortening the data-line pitch and using chain architecture to decrease the number of memory cells connecting to sense amplifiers , Toshiba maintained the same cell signal level without any chip area penalty. Furthermore, improvement of the sensing technique reduced the parasitic capacitance and realized a reading signal of 200mV, sufficient for practical application.

A circuit that can predict power fluctuation during read/write and control the power supply was also added. This new circuit realizes the voltage required for read and write, allowing the new FeRAM to add a DDR2 interface and opening the way to practical use.

Main specifications:

Process 130 nanometer CMOS
Density 128 megabits
Cell size 0.252 μm2
Read/ write speed (bandwidth) 1.6 gigabytes/second (DDR2 interface)
Cycle time 83 nanoseconds
Access time 43 nanoseconds
Power supply 1.8V

At the same event, Intel announced its latest developments in the SRAM memory. The company said that it has made an SRAM memory prototype with a density of 291 Mbits using the 32nm technology.

NEC also announced 32Mbit MRAM prototypes.


Previous
Next
AMD Announces Phenom II CPUs For DDR3        All News        Gigabyte at CeBIT 2009
SanDisk to Mass Produce 64GB Memory Cards     General Computing News      NEC Sharpens Image Quality With Super-Resolution ASSP

Get RSS feed Easy Print E-Mail this Message

Related News
Toshiba Announces 6TB Enterprise Cloud HDD
Toshiba Portege WT20 Business Tablet Now Available
Toshiba Introduces New Satellite Series Laptops, Fusion And Radius 2-In-1 PCs
Toshiba Develops Chip Authentication Technology Using Transistor Noise
Toshiba To License Its TV Business in Europe to Compal
Toshiba Develops SSD Simulation Platform
Toshiba Partners with Microsoft to Deliver New Internet of Things Solutions
Toshiba Demonstrates Object Storage Technologies
Toshiba Launches Application Processor Development Platforms for Wearable and IoT Devices
Toshiba Starts Mass Production of 13 Megapixel CMOS Image Sensor
Toshiba Announces the Portégé R30 laptop
Toshiba's Image Processing Technology Provides Image Quality on Par with Larger Sensors

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2015 - All rights reserved -
Privacy policy - Contact Us .