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Monday, February 25, 2008
Intel Packs 3 Dual-cores, 16MB L3 Cache in New "Dunnington" Processor


While AMD's quad-core Barcelona chip is trying to find its way to the market, Intel appears to have already designed a six-core CPU for this year.

The information "leaked" when presentation material appeared online at Sun Microsystems' website last weekend, and they were put offline some hours later.

According to the presentation, "Dunnington processors will follow Intel's Tigerton Xeon. The new chips will be the Intel's first to feature three processor pairs, each sharing 3MBs L2 cache. The chips will also be pin-compatible with Tigerton and will offer support for Intel's current Clarksboro chipset. They are supposed to appear in 2H of this year.

Dunnington should be considered to be interim to Intel's Nehalem chips, expected to debut early next year. The Nehalem architecture will be the first Intel processor to use the QuickPath Interconnect system architecture. Quickpath will include integrated memory controller technology and improved communication links between system components to significantly improve overall system performance.

ZDNet blogger George Ou, claims that the slides also contain some benchmarks for Nehalem and other processors. Ou estimates Nehalem's SPEC*fp_rate_base2006 at 163 and the SPEC*int_rate_base2006 at 176.

Intel did not comment on the supposed leak of the presentation slides.


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