IBM is expected to push its next-generation Power6 dual-core processors to run at higher speeds, rather than following the Intel/AMD concept for high-end computing that packs more cores on a die.
The nee CPU will run at speeds between 4-5GHz with a total of 8Mbytes L2 cache and a 75Gbyte/second link to external memory, according to EETImes.com.
The Power6 doubles the frequency and bandwidth of the existing Power5 without increasing its power consumption or the depth of its execution pipeline. The move lets IBM ship the chip as a mid-2007 refresh for its existing p-series server line.
"We needed to scale the whole system. When you just pack on more cores and don't scale the cache and memory bandwidth you can't really scale CPU performance as well," said Brad McCredie, a fellow in IBM's Systems and Technology Group.
The Power6 will essentially follow the pattern set by IBM with the Power4 and 5 CPUs. The Power4 was among the first computer CPUs to put two cores on a single die. The company packed two dice on a single module for high-end versions of the chip. Intel likewise plans to use multi-chip modules to pack two dual-core dice on a family of quad-core chip modules it will start introducing in November.
IBM's move to higher frequencies in its next-generation designs is a departure from the strategy of its competitor Sun Microsystems Inc., which has focused on moving to multicore processors and lower clock speeds as a way to keep power and heat in check. IBM may also surpass Intel in the speed race, although it has not determined exact speeds for shipping parts yet. Intel currently ships versions of its single-core Pentium running at up to 3.8GHz, but it slows its dual-core CPUs down to 2.93GHz or less.
Thus the big news for IBM is how it can double frequency while holding the line on power consumption and pipeline depth. New circuit designs and process technology improvements plow the way for the advances.
The processor is built in a 65-nm process using IBM's silicon-on-insulator (SOI) and strained silicon technology. IBM applied new techniques in variable gate lengths and variable threshold voltages to squeeze maximum performance per Watt at the transistor level. The chip can be fully operated at as little as 0.8V.
In addition, IBM will link its Power CPU for the first time to an external embedded controller. The controller will monitor and adjust power and performance parameters on the CPU based on set power management policies.
IBM is now in a systems test and debug phase using the Power6 in high-end, midrange and cluster computers for its p-series servers.