Fujitsu Laboratories Limited has developed a core circuitry technology for video compression and decompression that features quality video processingwith ultra-low power consumption of less than 100 milliwatts.

The new technology enables prolonged recording of high-quality video for digital devices that employ flash memory or hard-disk drives (HDDs) for recording, such as digital cameras and video camcorders. Fujitsu's new video compression and decompression technology conforms to the latest H.264 international standard for video compression, which is expected to attract wide attention in the future for next-generation DVDs and terrestrial digital broadcasting for mobile devices.

H.264 is more complex compared to former compression methods, and is known for requiring processing power that is approximately 10 times that which is required for MPEG-2.

To perceive changes in moving images from the previous image shown, a function which requires the greatest processing power during compression, rather than searching the entire picture for changes, Fujitsu developed an algorithm that enables image changes to be determined while searching shrunken versions of the picture in stages. This method enables minimal calculation volume, ideal for use in large-scale integrated circuits (LSIs), and enables real-time H.264 compression of standard television images at less than 100 milliwatts.

Fujitsu also developed an algorithm that enables control of compression levels, so that images for which image degradation is particularly obvious to human sight - such as faces or slow-moving objects - are continuously tracked, and those parts of the image are maintained at high definition and remain uncompressed.

Fujitsu's new technology is claimed to enable prolonged high-quality video recording using H.264 with battery-operated digital video devices.

Fujitsu will commercialize the technology by the end of 2006.

Key Specifications of Core Circuitry

- Functions: H.264/AVC compatible video compression & decompression
- Profile/level: Main profile at level 3.0
- Maximum screen size: 720 pixels x 576 lines (approx. equivalent to standard TVs)
- Operation clock: 54MHz (memory I/F: 108MHz)
- Circuit scale: Approximately 2 million gates
P- ower consumption: Less than 100 milliwatts (when used with a 90nm processor)