TSMC To Launch 3-D IC Assembly in 2013
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) will announce 3-D IC assembly service as a general offering at the beginning of next year.
The technology is called COWOS, standing for chip on wafer on substrate, Maria Marced, president of TSMC Europe, told the EETimes web site.
TSMC is already working with companies on the use of silicon interposer layers to carry multiple die. However, when the 3-D IC assembly service is offered TSMC plans that for most customers the 3-D assembly is done by TSMC.
3-D IC packaging allows for using wide I/O DRAM, which relieves bandwidth issues and reduced energy consumption.
The use of multiple die in components would likely change the nature of IC logic and SoC design. It would allow different functions to be developed on different optimized processes and brought together making use of through silicon vias (TSVs) created in thinned wafers. TSMC is offering a TSV-first approach to 3-D IC stacking.
TSMC is already working with companies on the use of silicon interposer layers to carry multiple die. However, when the 3-D IC assembly service is offered TSMC plans that for most customers the 3-D assembly is done by TSMC.
3-D IC packaging allows for using wide I/O DRAM, which relieves bandwidth issues and reduced energy consumption.
The use of multiple die in components would likely change the nature of IC logic and SoC design. It would allow different functions to be developed on different optimized processes and brought together making use of through silicon vias (TSVs) created in thinned wafers. TSMC is offering a TSV-first approach to 3-D IC stacking.
