Panasonic and Renesas to Collaborate on Development of SoCs at 32-nm Process Node
Building on their partnership<
The two companies are confident that their 32-nm node transistor technology and other advances can soon be applied to products in mass production.
It is anticipated that SoCs at the 32-nm node will deliver lower cost and improved performance enabled by miniaturization of their design rules, yet there are many technical issues that need to be solved. In particular, it is necessary to introduce new materials and develop new technologies to break through barriers to further integration, such as transistor gate leakage and inconsistent electrical characteristic problems, which are often found in existing technologies. Introducing new materials is technically difficult; however, the technology challenges in achieving acceptable transistor performance at the 32-nm node are more formidable than they were at previous-generation process nodes.
To meet these challenges, the new 32-nm SoC process employs a newly developed transistor technology with a metal/high-k1 gate stack structure and interconnect technology, using a new ultra-low-k2 material. To achieve a device using complementary metal-insulator semiconductor (CMIS)3 technology, a type of complementary Metal Oxide Semiconductor (CMOS), at a 32-nm node, an ultrathin film cap layer4 is applied at the atomic level to transistors with a metal/high-k gate stack structure under optimized conditions. This allows development of a conventional transistor configuration, employing an oxidized silicon film as the gate insulation layer. The introduction of the cap layer has been shown to improve transistor reliability in practical use and suppress distribution of electrical characteristics between transistors, thereby enabling the operation of large-scale circuits.
Panasonic and Reneasas have already jointly developed a 45-nm SoC process in 2007. The latest development on the new 32-nm fabrication process will be applied to SoCs for advanced mobile and digital home appliance products.
It is anticipated that SoCs at the 32-nm node will deliver lower cost and improved performance enabled by miniaturization of their design rules, yet there are many technical issues that need to be solved. In particular, it is necessary to introduce new materials and develop new technologies to break through barriers to further integration, such as transistor gate leakage and inconsistent electrical characteristic problems, which are often found in existing technologies. Introducing new materials is technically difficult; however, the technology challenges in achieving acceptable transistor performance at the 32-nm node are more formidable than they were at previous-generation process nodes.
To meet these challenges, the new 32-nm SoC process employs a newly developed transistor technology with a metal/high-k1 gate stack structure and interconnect technology, using a new ultra-low-k2 material. To achieve a device using complementary metal-insulator semiconductor (CMIS)3 technology, a type of complementary Metal Oxide Semiconductor (CMOS), at a 32-nm node, an ultrathin film cap layer4 is applied at the atomic level to transistors with a metal/high-k gate stack structure under optimized conditions. This allows development of a conventional transistor configuration, employing an oxidized silicon film as the gate insulation layer. The introduction of the cap layer has been shown to improve transistor reliability in practical use and suppress distribution of electrical characteristics between transistors, thereby enabling the operation of large-scale circuits.
Panasonic and Reneasas have already jointly developed a 45-nm SoC process in 2007. The latest development on the new 32-nm fabrication process will be applied to SoCs for advanced mobile and digital home appliance products.
