The CCIX Consortium today released the CCIX Base Specification 1.0, which enables a new class of high performance, low latency cache coherent interconnect for the cloud, artificial intelligence, big data, database and other datacenter infrastructures.
The growth of data combined with the demand for scalable compute-intensive applications, require the development of new compute, networking and storage platforms. These platforms will utilize highly efficient heterogeneous computing architectures that combine general purpose compute and accelerators such as GPUs, FPGAs, Smart NICs, Persistent Memory and other domain-specific programmable devices.
The CCIX Base Specification 1.0 defines a chip-to-chip interconnect for data sharing between compute, accelerators and memory expansion devices with cache coherent shared virtual memory. The specification leverages the PCI Express 4.0 architecture and ecosystem while increasing the throughput to 25GT/s per lane. Moreover, the specification adds the ability to maintain cache coherency across devices from different providers, to address the needs of heterogeneous compute systems, while enabling acceleration between them.
The benefits of CCIX include autonomous data movement between processor cache and accelerator cache without software driver involvement and the enablement of Cache Coherent Shared Virtual Memory programming paradigm.
The Base Specification 1.0 is available today for all CCIX members.