Intel Itanium Ahead of Dual-Core Debut
Intel decided to improve the speed of the front-side bus on its Itanium 2 processor, in preparation for the launch of its first dual-core Itanium processors.
The company will announce two new Itanium 2 processors on Monday with Hitachi,
which demonstrated a chip set that supported a 667MHz front-side bus at the
Spring Intel Developer Forum in March. One processor will be available with 9MB
of Level 3 cache memory, while the other will come with 6MB of cache memory.
Both chips will run at 1.66GHz, as infoworld.com reports.
Itanium is a 64-bit processor based on an entirely different instruction set than the x86 instruction set used by the vast majority of the world's PCs and servers. Intel had originally hoped Itanium and its EPIC (explicitly parallel instruction computing) instruction set would help it usher in the 64-bit era in server computing, but tepid customer reaction in the first five years of its existence has led Intel to target the chip as a high-end replacement for older servers using RISC (reduced instruction set computing) processors.
Improving Itanium's front-side bus speed will help the chip's performance on applications that require large amounts of data shuffled from the main memory to the CPU, said Kevin Krewell, editor in chief of The Microprocessor Report in San Jose, California. The enhancement will have implications on Intel's upcoming dual-core Itanium processor, code-named Montecito, which is expected in the fourth quarter, he said.
Montecito consists of two Itanium processor cores that will share a single front-side bus in some server designs, or take advantage of dual-independent buses in others. With all those extra processing resources competing for the same pathway to the memory, Intel needed to improve the speed of this link in order to take full advantage of both cores, Krewell said.
Itanium is primarily used in multiprocessor servers for high-performance computing or enterprise data centers. Hewlett-Packard is Intel's largest partner for Itanium, but Hitachi, Fujitsu, and IBM also dabble in the Itanium server market.
Itanium is a 64-bit processor based on an entirely different instruction set than the x86 instruction set used by the vast majority of the world's PCs and servers. Intel had originally hoped Itanium and its EPIC (explicitly parallel instruction computing) instruction set would help it usher in the 64-bit era in server computing, but tepid customer reaction in the first five years of its existence has led Intel to target the chip as a high-end replacement for older servers using RISC (reduced instruction set computing) processors.
Improving Itanium's front-side bus speed will help the chip's performance on applications that require large amounts of data shuffled from the main memory to the CPU, said Kevin Krewell, editor in chief of The Microprocessor Report in San Jose, California. The enhancement will have implications on Intel's upcoming dual-core Itanium processor, code-named Montecito, which is expected in the fourth quarter, he said.
Montecito consists of two Itanium processor cores that will share a single front-side bus in some server designs, or take advantage of dual-independent buses in others. With all those extra processing resources competing for the same pathway to the memory, Intel needed to improve the speed of this link in order to take full advantage of both cores, Krewell said.
Itanium is primarily used in multiprocessor servers for high-performance computing or enterprise data centers. Hewlett-Packard is Intel's largest partner for Itanium, but Hitachi, Fujitsu, and IBM also dabble in the Itanium server market.
