Micron And Broadcom Collaborate to Solve DRAM Timing Challenge
Micron Technology is working with Broadcom to develop a solution designed for their customers challenged by an intrinsic DDR3 timing parameter called tFAW, or four activate window.
tFAW refers to a DDR3 timing parameter that restricts data throughput in server, storage and networking applications and can compromise bandwidth by 15 to 35 percent. With every new DRAM generation, the access granularity is becoming double, causing some timing parameters like tRDD and tFAW to restrict data throughput. This creates challenges for high-performance applications because no more than four bank activate commands can be issued in any given tFAW period.
"The search for improved performance among network providers remains a challenge in the midst of continuous data overload," said Mike Howard, senior principal analyst of DRAM and memory at IHS iSuppli. "Architecture solutions that can open up bandwidth for high-performance applications will serve to extend operational efficiencies and boost overall network performance."
According to the Cisco Visual Networking Index, global IP traffic is projected to grow at a compound annual growth rate (CAGR) of 23 percent from 2012 to 2017.
To satisfy this appetite for bandwidth, service providers around the globe are racing to transform their networks by adopting higher-bandwidth links.
The Micron solution validated by Broadcom reduces the tFAW value from 35ns to 30ns for a 2KB page size, DDR3-2133, improving operations per second by 18 percent. This performance increase is especially critical for complex packet processing functions, such as highly scalable IPv4 and IPv6 lookups used in service provider networking applications. The four activate window solution enables Broadcom's BCM88030 200 Gb/s NPU to achieve scalable L2, IPv4 and IPv6 lookup capacities at wire speed performance using Micron's DDR3 memory.
Micron's 2Gb and 4Gb DDR3 with the reduced tFAW timing specification are available in volume production now.
"The search for improved performance among network providers remains a challenge in the midst of continuous data overload," said Mike Howard, senior principal analyst of DRAM and memory at IHS iSuppli. "Architecture solutions that can open up bandwidth for high-performance applications will serve to extend operational efficiencies and boost overall network performance."
According to the Cisco Visual Networking Index, global IP traffic is projected to grow at a compound annual growth rate (CAGR) of 23 percent from 2012 to 2017.
To satisfy this appetite for bandwidth, service providers around the globe are racing to transform their networks by adopting higher-bandwidth links.
The Micron solution validated by Broadcom reduces the tFAW value from 35ns to 30ns for a 2KB page size, DDR3-2133, improving operations per second by 18 percent. This performance increase is especially critical for complex packet processing functions, such as highly scalable IPv4 and IPv6 lookups used in service provider networking applications. The four activate window solution enables Broadcom's BCM88030 200 Gb/s NPU to achieve scalable L2, IPv4 and IPv6 lookup capacities at wire speed performance using Micron's DDR3 memory.
Micron's 2Gb and 4Gb DDR3 with the reduced tFAW timing specification are available in volume production now.
