Info on the Playstation 3 processor
IBM, Toshiba and Sony revealed some details about the new chip design.
At the Hot Chips conference Monday, chip designers from IBM and Toshiba revealed a few more details about the Cell processor, such as the structure of its internal and external connections as well as a co-processor designed to improve video performance.
Cell is a multicore processor designed in a three-way partnership between IBM, Toshiba and Sony, which is expected to use the chip in the Playstation 3 game console. The companies also envision the processor working in consumer devices like high-definition television recorders and enterprise computers like blade servers.
Cell will probably run at around 3.2GHz, a clock speed that presenters used twice in separate presentations as an example. The chip is based on IBM's Power architecture, but the heavy lifting is done by eight separate processing units called "synergistic processing elements," or SPEs.
Connecting those SPEs is an internal bus structure called the Element Interconnect Bus (EIB) that provides the "backbone" of Cell, said Scott Clark, a senior technical staff member with IBM. This bus actually uses several rings of interconnects that funnel data between the SPEs and both high-speed memory and I/O controllers needed to keep those units stuffed with data, he said.
The ElB can bring 16GB per second of data into Cell, and move 16GB of data out of the chip at the same time, Clark said.
That bandwidth can be only be fulfilled with the support of memory and I/O controllers designed by Rambus, said Kent Hasselhorst, also a senior technical staff member with IBM. Cell actually uses two on-chip memory controllers that support Rambus' XDR (extreme data rate) memory, he said.
Cell can theoretically support up to 64GB of memory, but the cost of implementing that much memory into consumer devices makes the practical memory configuration around 1GB or 2GB of XDR memory, Hasselhorst said.
Product designers can use Cell as a single chip or in multiple-chip configurations, Clark said. The chip's I/O bus allows Cell to be connected directly to another Cell chip. A separate switch is needed to connect separate groups of two Cell chips, he said.
Those designers could also attach a new chip developed by Toshiba called the "super companion chip" or SCC, according to Takayuka Mihara, a presenter with Toshiba. Consumer devices that need additional support for video decoding can attach the SCC to Cell's I/O port and decode up to 48 separate standard-definition video streams on a single device, according to a demonstration given by Mihara.
Source: [DigitMag]
Cell is a multicore processor designed in a three-way partnership between IBM, Toshiba and Sony, which is expected to use the chip in the Playstation 3 game console. The companies also envision the processor working in consumer devices like high-definition television recorders and enterprise computers like blade servers.
Cell will probably run at around 3.2GHz, a clock speed that presenters used twice in separate presentations as an example. The chip is based on IBM's Power architecture, but the heavy lifting is done by eight separate processing units called "synergistic processing elements," or SPEs.
Connecting those SPEs is an internal bus structure called the Element Interconnect Bus (EIB) that provides the "backbone" of Cell, said Scott Clark, a senior technical staff member with IBM. This bus actually uses several rings of interconnects that funnel data between the SPEs and both high-speed memory and I/O controllers needed to keep those units stuffed with data, he said.
The ElB can bring 16GB per second of data into Cell, and move 16GB of data out of the chip at the same time, Clark said.
That bandwidth can be only be fulfilled with the support of memory and I/O controllers designed by Rambus, said Kent Hasselhorst, also a senior technical staff member with IBM. Cell actually uses two on-chip memory controllers that support Rambus' XDR (extreme data rate) memory, he said.
Cell can theoretically support up to 64GB of memory, but the cost of implementing that much memory into consumer devices makes the practical memory configuration around 1GB or 2GB of XDR memory, Hasselhorst said.
Product designers can use Cell as a single chip or in multiple-chip configurations, Clark said. The chip's I/O bus allows Cell to be connected directly to another Cell chip. A separate switch is needed to connect separate groups of two Cell chips, he said.
Those designers could also attach a new chip developed by Toshiba called the "super companion chip" or SCC, according to Takayuka Mihara, a presenter with Toshiba. Consumer devices that need additional support for video decoding can attach the SCC to Cell's I/O port and decode up to 48 separate standard-definition video streams on a single device, according to a demonstration given by Mihara.
Source: [DigitMag]
