Fujitsu Develops Multi-Layer Interconnect Technology for 32nm Logic LSI Devices
Fujitsu Laboratories Ltd. and Fujitsu Limited today announced their development of technology that enables high-reliability multi-layer interconnects for logic LSIs for 32nm generation and beyond.
The new technology uses copper with manganese additives in combination with an ultra-thin film barrier metal. Compared to conventional technology, Fujitsu's new technology reduces line resistance in interconnects, and increases endurance against electro-migration - a cause of LSI degradation over time. Fujitsu claims that the new technology will enable production of highly-integrated high-performance LSIs.
Details of this technology were presented at the IEDM (International Electron Devices Meeting), held from December 10 - 12 in Washington, D.C..
There is a growing demand for high-performance, logic LSI devices that feature higher levels of integration and consume less power, a trend that is also driving the development of finer interconnects used in LSI devices. For example, the 32nm generation of logic LSIs that are currently under development will be using copper interconnects measuring 50nm wide. In order to enable the development of higher-performance LSIs, technology capable of achieving high reliability becomes necessary, by limiting the rise of interconnect resistance while in addition reducing age degradation of interconnects.
Up through the 45nm generation of LSIs, copper interconnects were wrapped in a barrier metal for protection. The barrier metal is necessary to prevent the diffusion of copper into the insulating film, and to prevent the insulating film from oxidizing the copper. A thick barrier metal improves reliability, but at the 32nm generation level of miniaturization, the barrier metal would occupy a disproportionate amount of space relative to the copper interconnect, thereby increasing the line resistance of the interconnect. Thus, the need to reduce line resistance while maintaining reliability has become a pressing issue.
By forming copper with manganese additives on an ultra-thin film barrier metal, Fujitsu succeeded in reducing interconnect line resistance, while maintaining high reliability. This interconnect structure (see Figure 1) is formed through the following processes:
- An ultra-thin film barrier metal is formed on the insulating layer to prevent copper diffusion.
- A seed layer of copper containing manganese is formed and then plated with the copper interconnect material.
In a following process, the structure is heated to a temperature above 350 degrees Celsius, which creates a manganese segregation layer - thinner than the barrier metal ? that enwraps the copper interconnects.
The use of a manganese segregation layer has made it possible to maintain existing barrier performance, as it prevents oxidation of the ultra-thin film barrier metal.
Compared to the copper interconnect barrier metal combination method that had been used up to the 45nm generation, this new technique from Fujitsu for multi-layer interconnects enables the reduction of thickness of barrier-metal films by one-third, and effectively reduces interconnect line resistance to levels that meet the standards laid out for the 32nm generation. In addition, by increasing endurance lifetime against electro-migration ? a cause for degradation over time - by a factor of 47, high reliability applicable for highly integrated minute interconnects for the 32nm generation and beyond is achieved.
This new technology paves the way for multi-layer interconnect technology applicable for logic LSIs for the 32nm generation and beyond. Fujitsu plans to further develop this technology to provide high-performance highly integrated power efficient LSIs.
Details of this technology were presented at the IEDM (International Electron Devices Meeting), held from December 10 - 12 in Washington, D.C..
There is a growing demand for high-performance, logic LSI devices that feature higher levels of integration and consume less power, a trend that is also driving the development of finer interconnects used in LSI devices. For example, the 32nm generation of logic LSIs that are currently under development will be using copper interconnects measuring 50nm wide. In order to enable the development of higher-performance LSIs, technology capable of achieving high reliability becomes necessary, by limiting the rise of interconnect resistance while in addition reducing age degradation of interconnects.
Up through the 45nm generation of LSIs, copper interconnects were wrapped in a barrier metal for protection. The barrier metal is necessary to prevent the diffusion of copper into the insulating film, and to prevent the insulating film from oxidizing the copper. A thick barrier metal improves reliability, but at the 32nm generation level of miniaturization, the barrier metal would occupy a disproportionate amount of space relative to the copper interconnect, thereby increasing the line resistance of the interconnect. Thus, the need to reduce line resistance while maintaining reliability has become a pressing issue.
By forming copper with manganese additives on an ultra-thin film barrier metal, Fujitsu succeeded in reducing interconnect line resistance, while maintaining high reliability. This interconnect structure (see Figure 1) is formed through the following processes:
- An ultra-thin film barrier metal is formed on the insulating layer to prevent copper diffusion.
- A seed layer of copper containing manganese is formed and then plated with the copper interconnect material.
In a following process, the structure is heated to a temperature above 350 degrees Celsius, which creates a manganese segregation layer - thinner than the barrier metal ? that enwraps the copper interconnects.
The use of a manganese segregation layer has made it possible to maintain existing barrier performance, as it prevents oxidation of the ultra-thin film barrier metal.
Compared to the copper interconnect barrier metal combination method that had been used up to the 45nm generation, this new technique from Fujitsu for multi-layer interconnects enables the reduction of thickness of barrier-metal films by one-third, and effectively reduces interconnect line resistance to levels that meet the standards laid out for the 32nm generation. In addition, by increasing endurance lifetime against electro-migration ? a cause for degradation over time - by a factor of 47, high reliability applicable for highly integrated minute interconnects for the 32nm generation and beyond is achieved.
This new technology paves the way for multi-layer interconnect technology applicable for logic LSIs for the 32nm generation and beyond. Fujitsu plans to further develop this technology to provide high-performance highly integrated power efficient LSIs.
